//
// Generated by Bluespec Compiler, version 2006.11 (build 9629, 2006-11-11)
// 
// On Mon Feb 12 20:57:37 EST 2007
// 
// Method conflict info:
// Method: initiator_0_request_put
// Conflict-free: initiator_0_response_get,
// 	       initiator_1_request_put,
// 	       initiator_1_response_get,
// 	       target_0_response_put,
// 	       target_1_response_put
// Sequenced after (restricted): target_0_request_get, target_1_request_get
// Conflicts: initiator_0_request_put
//  
// Method: initiator_0_response_get
// Conflict-free: initiator_0_request_put,
// 	       initiator_1_request_put,
// 	       initiator_1_response_get,
// 	       target_0_request_get,
// 	       target_1_request_get
// Sequenced after (restricted): target_0_response_put, target_1_response_put
// Conflicts: initiator_0_response_get
//  
// Method: initiator_1_request_put
// Conflict-free: initiator_0_request_put,
// 	       initiator_0_response_get,
// 	       initiator_1_response_get,
// 	       target_0_response_put,
// 	       target_1_response_put
// Sequenced after (restricted): target_0_request_get, target_1_request_get
// Conflicts: initiator_1_request_put
//  
// Method: initiator_1_response_get
// Conflict-free: initiator_0_request_put,
// 	       initiator_0_response_get,
// 	       initiator_1_request_put,
// 	       target_0_request_get,
// 	       target_1_request_get
// Sequenced after (restricted): target_0_response_put, target_1_response_put
// Conflicts: initiator_1_response_get
//  
// Method: target_0_request_get
// Conflict-free: initiator_0_response_get,
// 	       initiator_1_response_get,
// 	       target_0_response_put,
// 	       target_1_request_get,
// 	       target_1_response_put
// Sequenced before (restricted): initiator_0_request_put,
// 			       initiator_1_request_put
// Conflicts: target_0_request_get
//  
// Method: target_0_response_put
// Conflict-free: initiator_0_request_put,
// 	       initiator_1_request_put,
// 	       target_0_request_get,
// 	       target_1_request_get,
// 	       target_1_response_put
// Sequenced before (restricted): initiator_0_response_get,
// 			       initiator_1_response_get
// Conflicts: target_0_response_put
//  
// Method: target_1_request_get
// Conflict-free: initiator_0_response_get,
// 	       initiator_1_response_get,
// 	       target_0_request_get,
// 	       target_0_response_put,
// 	       target_1_response_put
// Sequenced before (restricted): initiator_0_request_put,
// 			       initiator_1_request_put
// Conflicts: target_1_request_get
//  
// Method: target_1_response_put
// Conflict-free: initiator_0_request_put,
// 	       initiator_1_request_put,
// 	       target_0_request_get,
// 	       target_0_response_put,
// 	       target_1_request_get
// Sequenced before (restricted): initiator_0_response_get,
// 			       initiator_1_response_get
// Conflicts: target_1_response_put
//  
// 
// Ports:
// Name                         I/O  size props
// RDY_initiator_0_request_put    O     1
// initiator_0_response_get       O    44
// RDY_initiator_0_response_get   O     1
// RDY_initiator_1_request_put    O     1
// initiator_1_response_get       O    44
// RDY_initiator_1_response_get   O     1
// target_0_request_get           O    76 reg
// RDY_target_0_request_get       O     1 reg
// RDY_target_0_response_put      O     1
// target_1_request_get           O    76 reg
// RDY_target_1_request_get       O     1 reg
// RDY_target_1_response_put      O     1
// CLK                            I     1
// RST_N                          I     1
// initiator_0_request_put        I    76
// initiator_1_request_put        I    76
// target_0_response_put          I    44
// target_1_response_put          I    44
// EN_initiator_0_request_put     I     1
// EN_initiator_1_request_put     I     1
// EN_target_0_response_put       I     1
// EN_target_1_response_put       I     1
// EN_initiator_0_response_get    I     1
// EN_initiator_1_response_get    I     1
// EN_target_0_request_get        I     1
// EN_target_1_request_get        I     1
// 
// Combinational paths from inputs to outputs:
//   (target_0_response_put,
//    target_1_response_put,
//    EN_target_0_response_put,
//    EN_target_1_response_put) -> RDY_initiator_0_response_get
//   (target_0_response_put,
//    target_1_response_put,
//    EN_target_0_response_put,
//    EN_target_1_response_put) -> RDY_initiator_1_response_get
//   (target_0_response_put,
//    target_1_response_put,
//    EN_target_0_response_put,
//    EN_target_1_response_put) -> initiator_0_response_get
//   (target_0_response_put,
//    target_1_response_put,
//    EN_target_0_response_put,
//    EN_target_1_response_put) -> initiator_1_response_get
//   (EN_target_0_request_get,
//    EN_target_1_request_get) -> RDY_initiator_0_request_put
//   (EN_target_0_request_get,
//    EN_target_1_request_get) -> RDY_initiator_1_request_put
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkSwitch(CLK,
		RST_N,
		
		initiator_0_request_put,
		EN_initiator_0_request_put,
		RDY_initiator_0_request_put,
		
		EN_initiator_0_response_get,
		initiator_0_response_get,
		RDY_initiator_0_response_get,
		
		initiator_1_request_put,
		EN_initiator_1_request_put,
		RDY_initiator_1_request_put,
		
		EN_initiator_1_response_get,
		initiator_1_response_get,
		RDY_initiator_1_response_get,
		
		EN_target_0_request_get,
		target_0_request_get,
		RDY_target_0_request_get,
		
		target_0_response_put,
		EN_target_0_response_put,
		RDY_target_0_response_put,
		
		EN_target_1_request_get,
		target_1_request_get,
		RDY_target_1_request_get,
		
		target_1_response_put,
		EN_target_1_response_put,
		RDY_target_1_response_put);
  input  CLK;
  input  RST_N;
  
  // action method initiator_0_request_put
  input  [75 : 0] initiator_0_request_put;
  input  EN_initiator_0_request_put;
  output RDY_initiator_0_request_put;
  
  // actionvalue method initiator_0_response_get
  input  EN_initiator_0_response_get;
  output [43 : 0] initiator_0_response_get;
  output RDY_initiator_0_response_get;
  
  // action method initiator_1_request_put
  input  [75 : 0] initiator_1_request_put;
  input  EN_initiator_1_request_put;
  output RDY_initiator_1_request_put;
  
  // actionvalue method initiator_1_response_get
  input  EN_initiator_1_response_get;
  output [43 : 0] initiator_1_response_get;
  output RDY_initiator_1_response_get;
  
  // actionvalue method target_0_request_get
  input  EN_target_0_request_get;
  output [75 : 0] target_0_request_get;
  output RDY_target_0_request_get;
  
  // action method target_0_response_put
  input  [43 : 0] target_0_response_put;
  input  EN_target_0_response_put;
  output RDY_target_0_response_put;
  
  // actionvalue method target_1_request_get
  input  EN_target_1_request_get;
  output [75 : 0] target_1_request_get;
  output RDY_target_1_request_get;
  
  // action method target_1_response_put
  input  [43 : 0] target_1_response_put;
  input  EN_target_1_response_put;
  output RDY_target_1_response_put;

  // signals for module outputs
  wire [75 : 0] target_0_request_get, target_1_request_get;
  wire [43 : 0] initiator_0_response_get, initiator_1_response_get;
  wire RDY_initiator_0_request_put,
       RDY_initiator_0_response_get,
       RDY_initiator_1_request_put,
       RDY_initiator_1_response_get,
       RDY_target_0_request_get,
       RDY_target_0_response_put,
       RDY_target_1_request_get,
       RDY_target_1_response_put;

  // inlined wires
  reg [75 : 0] to_target_0_rw_enq$wget, to_target_1_rw_enq$wget;
  reg [43 : 0] to_initiator_0_rw_enq$wget;
  wire from_initiator_0_pw_deq$whas,
       from_initiator_1_pw_deq$whas,
       to_initiator_0_rw_enq$whas,
       to_initiator_1_rw_enq$whas,
       to_target_0_rw_enq$whas,
       to_target_1_rw_enq$whas;

  // register from_initiator_0_taggedReg
  reg [76 : 0] from_initiator_0_taggedReg;
  wire [76 : 0] from_initiator_0_taggedReg$D_IN;
  wire from_initiator_0_taggedReg$EN;

  // register from_initiator_1_taggedReg
  reg [76 : 0] from_initiator_1_taggedReg;
  wire [76 : 0] from_initiator_1_taggedReg$D_IN;
  wire from_initiator_1_taggedReg$EN;

  // register from_target_0_taggedReg
  reg [44 : 0] from_target_0_taggedReg;
  wire [44 : 0] from_target_0_taggedReg$D_IN;
  wire from_target_0_taggedReg$EN;

  // register from_target_1_taggedReg
  reg [44 : 0] from_target_1_taggedReg;
  wire [44 : 0] from_target_1_taggedReg$D_IN;
  wire from_target_1_taggedReg$EN;

  // register to_initiator_0_round_robin
  reg to_initiator_0_round_robin;
  wire to_initiator_0_round_robin$D_IN, to_initiator_0_round_robin$EN;

  // register to_initiator_0_taggedReg
  reg [44 : 0] to_initiator_0_taggedReg;
  wire [44 : 0] to_initiator_0_taggedReg$D_IN;
  wire to_initiator_0_taggedReg$EN;

  // register to_initiator_1_round_robin
  reg to_initiator_1_round_robin;
  wire to_initiator_1_round_robin$D_IN, to_initiator_1_round_robin$EN;

  // register to_initiator_1_taggedReg
  reg [44 : 0] to_initiator_1_taggedReg;
  wire [44 : 0] to_initiator_1_taggedReg$D_IN;
  wire to_initiator_1_taggedReg$EN;

  // register to_target_0_round_robin
  reg to_target_0_round_robin;
  wire to_target_0_round_robin$D_IN, to_target_0_round_robin$EN;

  // register to_target_0_taggedReg
  reg [76 : 0] to_target_0_taggedReg;
  wire [76 : 0] to_target_0_taggedReg$D_IN;
  wire to_target_0_taggedReg$EN;

  // register to_target_1_round_robin
  reg to_target_1_round_robin;
  wire to_target_1_round_robin$D_IN, to_target_1_round_robin$EN;

  // register to_target_1_taggedReg
  reg [76 : 0] to_target_1_taggedReg;
  wire [76 : 0] to_target_1_taggedReg$D_IN;
  wire to_target_1_taggedReg$EN;

  // rule scheduling signals
  wire CAN_FIRE_RL_both_initiators_to_target_0,
       CAN_FIRE_RL_both_initiators_to_target_1,
       CAN_FIRE_RL_both_targets_to_initiator_0,
       CAN_FIRE_RL_both_targets_to_initiator_1,
       CAN_FIRE_RL_from_initiator_0_rule_update_final,
       CAN_FIRE_RL_from_initiator_1_rule_update_final,
       CAN_FIRE_RL_from_target_0_rule_deq,
       CAN_FIRE_RL_from_target_0_rule_enq,
       CAN_FIRE_RL_from_target_1_rule_deq,
       CAN_FIRE_RL_from_target_1_rule_enq,
       CAN_FIRE_RL_initiator_0_to_target_0,
       CAN_FIRE_RL_initiator_0_to_target_1,
       CAN_FIRE_RL_initiator_1_to_target_0,
       CAN_FIRE_RL_initiator_1_to_target_1,
       CAN_FIRE_RL_target_0_to_initiator_0,
       CAN_FIRE_RL_target_0_to_initiator_1,
       CAN_FIRE_RL_target_1_to_initiator_0,
       CAN_FIRE_RL_target_1_to_initiator_1,
       CAN_FIRE_RL_to_initiator_0_rule_deq,
       CAN_FIRE_RL_to_initiator_0_rule_enq,
       CAN_FIRE_RL_to_initiator_1_rule_deq,
       CAN_FIRE_RL_to_initiator_1_rule_enq,
       CAN_FIRE_RL_to_target_0_rule_update_final,
       CAN_FIRE_RL_to_target_1_rule_update_final,
       CAN_FIRE_initiator_0_request_put,
       CAN_FIRE_initiator_0_response_get,
       CAN_FIRE_initiator_1_request_put,
       CAN_FIRE_initiator_1_response_get,
       CAN_FIRE_target_0_request_get,
       CAN_FIRE_target_0_response_put,
       CAN_FIRE_target_1_request_get,
       CAN_FIRE_target_1_response_put,
       WILL_FIRE_RL_both_initiators_to_target_0,
       WILL_FIRE_RL_both_initiators_to_target_1,
       WILL_FIRE_RL_both_targets_to_initiator_0,
       WILL_FIRE_RL_both_targets_to_initiator_1,
       WILL_FIRE_RL_from_initiator_0_rule_update_final,
       WILL_FIRE_RL_from_initiator_1_rule_update_final,
       WILL_FIRE_RL_from_target_0_rule_deq,
       WILL_FIRE_RL_from_target_0_rule_enq,
       WILL_FIRE_RL_from_target_1_rule_deq,
       WILL_FIRE_RL_from_target_1_rule_enq,
       WILL_FIRE_RL_initiator_0_to_target_0,
       WILL_FIRE_RL_initiator_0_to_target_1,
       WILL_FIRE_RL_initiator_1_to_target_0,
       WILL_FIRE_RL_initiator_1_to_target_1,
       WILL_FIRE_RL_target_0_to_initiator_0,
       WILL_FIRE_RL_target_0_to_initiator_1,
       WILL_FIRE_RL_target_1_to_initiator_0,
       WILL_FIRE_RL_target_1_to_initiator_1,
       WILL_FIRE_RL_to_initiator_0_rule_deq,
       WILL_FIRE_RL_to_initiator_0_rule_enq,
       WILL_FIRE_RL_to_initiator_1_rule_deq,
       WILL_FIRE_RL_to_initiator_1_rule_enq,
       WILL_FIRE_RL_to_target_0_rule_update_final,
       WILL_FIRE_RL_to_target_1_rule_update_final,
       WILL_FIRE_initiator_0_request_put,
       WILL_FIRE_initiator_0_response_get,
       WILL_FIRE_initiator_1_request_put,
       WILL_FIRE_initiator_1_response_get,
       WILL_FIRE_target_0_request_get,
       WILL_FIRE_target_0_response_put,
       WILL_FIRE_target_1_request_get,
       WILL_FIRE_target_1_response_put;

  // inputs to muxes for submodule ports
  wire [75 : 0] MUX_to_target_0_rw_enq$wset_1__VAL_1,
		MUX_to_target_1_rw_enq$wset_1__VAL_1;
  wire [44 : 0] MUX_from_target_0_taggedReg$write_1__VAL_1,
		MUX_from_target_1_taggedReg$write_1__VAL_1,
		MUX_to_initiator_0_taggedReg$write_1__VAL_1,
		MUX_to_initiator_1_taggedReg$write_1__VAL_1;
  wire [43 : 0] MUX_to_initiator_0_rw_enq$wset_1__VAL_1,
		MUX_to_initiator_1_rw_enq$wset_1__VAL_1;

  // remaining internal signals
  reg [43 : 0] _x__h664;
  wire [43 : 0] IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215,
		IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214;
  wire [42 : 0] IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d249,
		IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d248,
		IF_to_initiator_0_rw_enq_whas__50_THEN_to_init_ETC___d246,
		IF_to_initiator_1_rw_enq_whas__44_THEN_to_init_ETC___d244;
  wire [32 : 0] IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d251,
		IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d250;
  wire IF_from_target_0_rw_enq_whas__8_THEN_NOT_from__ETC___d203,
       IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205,
       IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d204,
       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d206,
       NOT_to_initiator_0_taggedReg_1_BIT_44_2_3_AND__ETC___d76,
       NOT_to_initiator_1_taggedReg_BIT_44_AND_from_t_ETC___d56,
       NOT_to_target_0_taggedReg_05_BIT_76_06_07_OR_t_ETC___d120;

  // action method initiator_0_request_put
  assign RDY_initiator_0_request_put =
	     !from_initiator_0_taggedReg[76] || from_initiator_0_pw_deq$whas ;
  assign WILL_FIRE_initiator_0_request_put = EN_initiator_0_request_put ;
  assign CAN_FIRE_initiator_0_request_put = EN_initiator_0_request_put ;

  // actionvalue method initiator_0_response_get
  assign RDY_initiator_0_response_get =
	     to_initiator_0_taggedReg[44] || to_initiator_0_rw_enq$whas ;
  assign initiator_0_response_get =
	     { to_initiator_0_rw_enq$whas ?
		 to_initiator_0_rw_enq$wget[43] :
		 to_initiator_0_taggedReg[43],
	       IF_to_initiator_0_rw_enq_whas__50_THEN_to_init_ETC___d246 } ;
  assign WILL_FIRE_initiator_0_response_get = EN_initiator_0_response_get ;
  assign CAN_FIRE_initiator_0_response_get = EN_initiator_0_response_get ;

  // action method initiator_1_request_put
  assign RDY_initiator_1_request_put =
	     !from_initiator_1_taggedReg[76] || from_initiator_1_pw_deq$whas ;
  assign WILL_FIRE_initiator_1_request_put = EN_initiator_1_request_put ;
  assign CAN_FIRE_initiator_1_request_put = EN_initiator_1_request_put ;

  // actionvalue method initiator_1_response_get
  assign RDY_initiator_1_response_get =
	     to_initiator_1_taggedReg[44] || to_initiator_1_rw_enq$whas ;
  assign initiator_1_response_get =
	     { to_initiator_1_rw_enq$whas ?
		 _x__h664[43] :
		 to_initiator_1_taggedReg[43],
	       IF_to_initiator_1_rw_enq_whas__44_THEN_to_init_ETC___d244 } ;
  assign WILL_FIRE_initiator_1_response_get = EN_initiator_1_response_get ;
  assign CAN_FIRE_initiator_1_response_get = EN_initiator_1_response_get ;

  // actionvalue method target_0_request_get
  assign target_0_request_get = to_target_0_taggedReg[75:0] ;
  assign RDY_target_0_request_get = to_target_0_taggedReg[76] ;
  assign WILL_FIRE_target_0_request_get = EN_target_0_request_get ;
  assign CAN_FIRE_target_0_request_get = EN_target_0_request_get ;

  // action method target_0_response_put
  assign RDY_target_0_response_put = !from_target_0_taggedReg[44] ;
  assign WILL_FIRE_target_0_response_put = EN_target_0_response_put ;
  assign CAN_FIRE_target_0_response_put = EN_target_0_response_put ;

  // actionvalue method target_1_request_get
  assign target_1_request_get = to_target_1_taggedReg[75:0] ;
  assign RDY_target_1_request_get = to_target_1_taggedReg[76] ;
  assign WILL_FIRE_target_1_request_get = EN_target_1_request_get ;
  assign CAN_FIRE_target_1_request_get = EN_target_1_request_get ;

  // action method target_1_response_put
  assign RDY_target_1_response_put = !from_target_1_taggedReg[44] ;
  assign WILL_FIRE_target_1_response_put = EN_target_1_response_put ;
  assign CAN_FIRE_target_1_response_put = EN_target_1_response_put ;

  // rule RL_both_initiators_to_target_0
  assign WILL_FIRE_RL_both_initiators_to_target_0 =
	     from_initiator_0_taggedReg[76] &&
	     NOT_to_target_0_taggedReg_05_BIT_76_06_07_OR_t_ETC___d120 &&
	     !from_initiator_0_taggedReg[32] &&
	     !from_initiator_1_taggedReg[32] ;
  assign CAN_FIRE_RL_both_initiators_to_target_0 =
	     WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_initiator_0_to_target_0
  assign CAN_FIRE_RL_initiator_0_to_target_0 =
	     from_initiator_0_taggedReg[76] &&
	     (!to_target_0_taggedReg[76] || EN_target_0_request_get) &&
	     !from_initiator_0_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_0_to_target_0 =
	     CAN_FIRE_RL_initiator_0_to_target_0 &&
	     !WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_both_initiators_to_target_1
  assign WILL_FIRE_RL_both_initiators_to_target_1 =
	     from_initiator_0_taggedReg[76] &&
	     (!to_target_1_taggedReg[76] || EN_target_1_request_get) &&
	     from_initiator_1_taggedReg[76] &&
	     from_initiator_0_taggedReg[32] &&
	     from_initiator_1_taggedReg[32] ;
  assign CAN_FIRE_RL_both_initiators_to_target_1 =
	     WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_initiator_0_to_target_1
  assign CAN_FIRE_RL_initiator_0_to_target_1 =
	     from_initiator_0_taggedReg[76] &&
	     (!to_target_1_taggedReg[76] || EN_target_1_request_get) &&
	     from_initiator_0_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_0_to_target_1 =
	     CAN_FIRE_RL_initiator_0_to_target_1 &&
	     !WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_initiator_1_to_target_0
  assign CAN_FIRE_RL_initiator_1_to_target_0 =
	     from_initiator_1_taggedReg[76] &&
	     (!to_target_0_taggedReg[76] || EN_target_0_request_get) &&
	     !from_initiator_1_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_1_to_target_0 =
	     CAN_FIRE_RL_initiator_1_to_target_0 &&
	     !WILL_FIRE_RL_initiator_0_to_target_0 &&
	     !WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_initiator_1_to_target_1
  assign CAN_FIRE_RL_initiator_1_to_target_1 =
	     from_initiator_1_taggedReg[76] &&
	     (!to_target_1_taggedReg[76] || EN_target_1_request_get) &&
	     from_initiator_1_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_1_to_target_1 =
	     CAN_FIRE_RL_initiator_1_to_target_1 &&
	     !WILL_FIRE_RL_initiator_0_to_target_1 &&
	     !WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_both_targets_to_initiator_0
  assign WILL_FIRE_RL_both_targets_to_initiator_0 =
	     NOT_to_initiator_0_taggedReg_1_BIT_44_2_3_AND__ETC___d76 &&
	     IF_from_target_0_rw_enq_whas__8_THEN_NOT_from__ETC___d203 &&
	     IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d204 ;
  assign CAN_FIRE_RL_both_targets_to_initiator_0 =
	     WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_target_0_to_initiator_0
  assign CAN_FIRE_RL_target_0_to_initiator_0 =
	     !to_initiator_0_taggedReg[44] &&
	     (from_target_0_taggedReg[44] || EN_target_0_response_put) &&
	     IF_from_target_0_rw_enq_whas__8_THEN_NOT_from__ETC___d203 ;
  assign WILL_FIRE_RL_target_0_to_initiator_0 =
	     CAN_FIRE_RL_target_0_to_initiator_0 &&
	     !WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_target_1_to_initiator_0
  assign CAN_FIRE_RL_target_1_to_initiator_0 =
	     !to_initiator_0_taggedReg[44] &&
	     (from_target_1_taggedReg[44] || EN_target_1_response_put) &&
	     IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d204 ;
  assign WILL_FIRE_RL_target_1_to_initiator_0 =
	     CAN_FIRE_RL_target_1_to_initiator_0 &&
	     !WILL_FIRE_RL_target_0_to_initiator_0 &&
	     !WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_both_targets_to_initiator_1
  assign WILL_FIRE_RL_both_targets_to_initiator_1 =
	     NOT_to_initiator_1_taggedReg_BIT_44_AND_from_t_ETC___d56 &&
	     IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205 &&
	     IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d206 ;
  assign CAN_FIRE_RL_both_targets_to_initiator_1 =
	     WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_target_0_to_initiator_1
  assign CAN_FIRE_RL_target_0_to_initiator_1 =
	     !to_initiator_1_taggedReg[44] &&
	     (from_target_0_taggedReg[44] || EN_target_0_response_put) &&
	     IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205 ;
  assign WILL_FIRE_RL_target_0_to_initiator_1 =
	     CAN_FIRE_RL_target_0_to_initiator_1 &&
	     !WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_target_1_to_initiator_1
  assign CAN_FIRE_RL_target_1_to_initiator_1 =
	     !to_initiator_1_taggedReg[44] &&
	     (from_target_1_taggedReg[44] || EN_target_1_response_put) &&
	     IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d206 ;
  assign WILL_FIRE_RL_target_1_to_initiator_1 =
	     CAN_FIRE_RL_target_1_to_initiator_1 &&
	     !WILL_FIRE_RL_target_0_to_initiator_1 &&
	     !WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_from_target_1_rule_deq
  assign WILL_FIRE_RL_from_target_1_rule_deq =
	     WILL_FIRE_RL_both_targets_to_initiator_0 &&
	     !to_initiator_0_round_robin ||
	     WILL_FIRE_RL_both_targets_to_initiator_1 &&
	     !to_initiator_1_round_robin ||
	     WILL_FIRE_RL_target_1_to_initiator_0 ||
	     WILL_FIRE_RL_target_1_to_initiator_1 ;
  assign CAN_FIRE_RL_from_target_1_rule_deq =
	     WILL_FIRE_RL_from_target_1_rule_deq ;

  // rule RL_from_target_1_rule_enq
  assign WILL_FIRE_RL_from_target_1_rule_enq =
	     EN_target_1_response_put &&
	     !WILL_FIRE_RL_from_target_1_rule_deq ;
  assign CAN_FIRE_RL_from_target_1_rule_enq =
	     WILL_FIRE_RL_from_target_1_rule_enq ;

  // rule RL_from_target_0_rule_deq
  assign WILL_FIRE_RL_from_target_0_rule_deq =
	     WILL_FIRE_RL_both_targets_to_initiator_1 &&
	     to_initiator_1_round_robin ||
	     WILL_FIRE_RL_both_targets_to_initiator_0 &&
	     to_initiator_0_round_robin ||
	     WILL_FIRE_RL_target_0_to_initiator_0 ||
	     WILL_FIRE_RL_target_0_to_initiator_1 ;
  assign CAN_FIRE_RL_from_target_0_rule_deq =
	     WILL_FIRE_RL_from_target_0_rule_deq ;

  // rule RL_from_target_0_rule_enq
  assign WILL_FIRE_RL_from_target_0_rule_enq =
	     EN_target_0_response_put &&
	     !WILL_FIRE_RL_from_target_0_rule_deq ;
  assign CAN_FIRE_RL_from_target_0_rule_enq =
	     WILL_FIRE_RL_from_target_0_rule_enq ;

  // rule RL_to_target_1_rule_update_final
  assign WILL_FIRE_RL_to_target_1_rule_update_final =
	     to_target_1_rw_enq$whas || EN_target_1_request_get ;
  assign CAN_FIRE_RL_to_target_1_rule_update_final =
	     WILL_FIRE_RL_to_target_1_rule_update_final ;

  // rule RL_to_target_0_rule_update_final
  assign WILL_FIRE_RL_to_target_0_rule_update_final =
	     to_target_0_rw_enq$whas || EN_target_0_request_get ;
  assign CAN_FIRE_RL_to_target_0_rule_update_final =
	     WILL_FIRE_RL_to_target_0_rule_update_final ;

  // rule RL_to_initiator_1_rule_deq
  assign WILL_FIRE_RL_to_initiator_1_rule_deq = EN_initiator_1_response_get ;
  assign CAN_FIRE_RL_to_initiator_1_rule_deq = EN_initiator_1_response_get ;

  // rule RL_to_initiator_1_rule_enq
  assign WILL_FIRE_RL_to_initiator_1_rule_enq =
	     to_initiator_1_rw_enq$whas && !EN_initiator_1_response_get ;
  assign CAN_FIRE_RL_to_initiator_1_rule_enq =
	     WILL_FIRE_RL_to_initiator_1_rule_enq ;

  // rule RL_to_initiator_0_rule_deq
  assign WILL_FIRE_RL_to_initiator_0_rule_deq = EN_initiator_0_response_get ;
  assign CAN_FIRE_RL_to_initiator_0_rule_deq = EN_initiator_0_response_get ;

  // rule RL_to_initiator_0_rule_enq
  assign WILL_FIRE_RL_to_initiator_0_rule_enq =
	     to_initiator_0_rw_enq$whas && !EN_initiator_0_response_get ;
  assign CAN_FIRE_RL_to_initiator_0_rule_enq =
	     WILL_FIRE_RL_to_initiator_0_rule_enq ;

  // rule RL_from_initiator_1_rule_update_final
  assign WILL_FIRE_RL_from_initiator_1_rule_update_final =
	     EN_initiator_1_request_put || from_initiator_1_pw_deq$whas ;
  assign CAN_FIRE_RL_from_initiator_1_rule_update_final =
	     WILL_FIRE_RL_from_initiator_1_rule_update_final ;

  // rule RL_from_initiator_0_rule_update_final
  assign WILL_FIRE_RL_from_initiator_0_rule_update_final =
	     EN_initiator_0_request_put || from_initiator_0_pw_deq$whas ;
  assign CAN_FIRE_RL_from_initiator_0_rule_update_final =
	     WILL_FIRE_RL_from_initiator_0_rule_update_final ;

  // inputs to muxes for submodule ports
  assign MUX_from_target_0_taggedReg$write_1__VAL_1 =
	     { 1'd1, target_0_response_put } ;
  assign MUX_from_target_1_taggedReg$write_1__VAL_1 =
	     { 1'd1, target_1_response_put } ;
  assign MUX_to_initiator_0_rw_enq$wset_1__VAL_1 =
	     to_initiator_0_round_robin ?
	       IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215 :
	       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214 ;
  assign MUX_to_initiator_1_rw_enq$wset_1__VAL_1 =
	     to_initiator_1_round_robin ?
	       IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215 :
	       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214 ;
  assign MUX_to_initiator_1_taggedReg$write_1__VAL_1 = { 1'd1, _x__h664 } ;
  assign MUX_to_target_0_rw_enq$wset_1__VAL_1 =
	     to_target_0_round_robin ?
	       from_initiator_0_taggedReg[75:0] :
	       from_initiator_1_taggedReg[75:0] ;
  assign MUX_to_target_1_rw_enq$wset_1__VAL_1 =
	     to_target_1_round_robin ?
	       from_initiator_0_taggedReg[75:0] :
	       from_initiator_1_taggedReg[75:0] ;
  assign MUX_to_initiator_0_taggedReg$write_1__VAL_1 =
	     { 1'd1, to_initiator_0_rw_enq$wget } ;

  // inlined wires
  assign from_initiator_0_pw_deq$whas =
	     WILL_FIRE_RL_both_initiators_to_target_1 &&
	     to_target_1_round_robin ||
	     WILL_FIRE_RL_both_initiators_to_target_0 &&
	     to_target_0_round_robin ||
	     WILL_FIRE_RL_initiator_0_to_target_0 ||
	     WILL_FIRE_RL_initiator_0_to_target_1 ;
  assign from_initiator_1_pw_deq$whas =
	     WILL_FIRE_RL_both_initiators_to_target_0 &&
	     !to_target_0_round_robin ||
	     WILL_FIRE_RL_both_initiators_to_target_1 &&
	     !to_target_1_round_robin ||
	     WILL_FIRE_RL_initiator_1_to_target_0 ||
	     WILL_FIRE_RL_initiator_1_to_target_1 ;
  always@(WILL_FIRE_RL_both_targets_to_initiator_0 or
	  MUX_to_initiator_0_rw_enq$wset_1__VAL_1 or
	  WILL_FIRE_RL_target_0_to_initiator_0 or
	  IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215 or
	  WILL_FIRE_RL_target_1_to_initiator_0 or
	  IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_targets_to_initiator_0:
	  to_initiator_0_rw_enq$wget =
	      MUX_to_initiator_0_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_target_0_to_initiator_0:
	  to_initiator_0_rw_enq$wget =
	      IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215;
      WILL_FIRE_RL_target_1_to_initiator_0:
	  to_initiator_0_rw_enq$wget =
	      IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214;
      default: to_initiator_0_rw_enq$wget =
		   44'hAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_initiator_0_rw_enq$whas =
	     WILL_FIRE_RL_both_targets_to_initiator_0 ||
	     WILL_FIRE_RL_target_0_to_initiator_0 ||
	     WILL_FIRE_RL_target_1_to_initiator_0 ;
  assign to_initiator_1_rw_enq$whas =
	     WILL_FIRE_RL_both_targets_to_initiator_1 ||
	     WILL_FIRE_RL_target_0_to_initiator_1 ||
	     WILL_FIRE_RL_target_1_to_initiator_1 ;
  always@(WILL_FIRE_RL_both_initiators_to_target_0 or
	  MUX_to_target_0_rw_enq$wset_1__VAL_1 or
	  WILL_FIRE_RL_initiator_0_to_target_0 or
	  from_initiator_0_taggedReg or
	  WILL_FIRE_RL_initiator_1_to_target_0 or from_initiator_1_taggedReg)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_initiators_to_target_0:
	  to_target_0_rw_enq$wget = MUX_to_target_0_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_initiator_0_to_target_0:
	  to_target_0_rw_enq$wget = from_initiator_0_taggedReg[75:0];
      WILL_FIRE_RL_initiator_1_to_target_0:
	  to_target_0_rw_enq$wget = from_initiator_1_taggedReg[75:0];
      default: to_target_0_rw_enq$wget =
		   76'hAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_target_0_rw_enq$whas =
	     WILL_FIRE_RL_both_initiators_to_target_0 ||
	     WILL_FIRE_RL_initiator_0_to_target_0 ||
	     WILL_FIRE_RL_initiator_1_to_target_0 ;
  always@(WILL_FIRE_RL_both_initiators_to_target_1 or
	  MUX_to_target_1_rw_enq$wset_1__VAL_1 or
	  WILL_FIRE_RL_initiator_0_to_target_1 or
	  from_initiator_0_taggedReg or
	  WILL_FIRE_RL_initiator_1_to_target_1 or from_initiator_1_taggedReg)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_initiators_to_target_1:
	  to_target_1_rw_enq$wget = MUX_to_target_1_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_initiator_0_to_target_1:
	  to_target_1_rw_enq$wget = from_initiator_0_taggedReg[75:0];
      WILL_FIRE_RL_initiator_1_to_target_1:
	  to_target_1_rw_enq$wget = from_initiator_1_taggedReg[75:0];
      default: to_target_1_rw_enq$wget =
		   76'hAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_target_1_rw_enq$whas =
	     WILL_FIRE_RL_both_initiators_to_target_1 ||
	     WILL_FIRE_RL_initiator_0_to_target_1 ||
	     WILL_FIRE_RL_initiator_1_to_target_1 ;

  // register from_initiator_0_taggedReg
  assign from_initiator_0_taggedReg$D_IN =
	     { EN_initiator_0_request_put, initiator_0_request_put } ;
  assign from_initiator_0_taggedReg$EN =
	     WILL_FIRE_RL_from_initiator_0_rule_update_final ;

  // register from_initiator_1_taggedReg
  assign from_initiator_1_taggedReg$D_IN =
	     { EN_initiator_1_request_put, initiator_1_request_put } ;
  assign from_initiator_1_taggedReg$EN =
	     WILL_FIRE_RL_from_initiator_1_rule_update_final ;

  // register from_target_0_taggedReg
  assign from_target_0_taggedReg$D_IN =
	     WILL_FIRE_RL_from_target_0_rule_enq ?
	       MUX_from_target_0_taggedReg$write_1__VAL_1 :
	       45'h0AAAAAAAAAAA ;
  assign from_target_0_taggedReg$EN =
	     WILL_FIRE_RL_from_target_0_rule_enq ||
	     WILL_FIRE_RL_from_target_0_rule_deq ;

  // register from_target_1_taggedReg
  assign from_target_1_taggedReg$D_IN =
	     WILL_FIRE_RL_from_target_1_rule_enq ?
	       MUX_from_target_1_taggedReg$write_1__VAL_1 :
	       45'h0AAAAAAAAAAA ;
  assign from_target_1_taggedReg$EN =
	     WILL_FIRE_RL_from_target_1_rule_enq ||
	     WILL_FIRE_RL_from_target_1_rule_deq ;

  // register to_initiator_0_round_robin
  assign to_initiator_0_round_robin$D_IN = !to_initiator_0_round_robin ;
  assign to_initiator_0_round_robin$EN =
	     WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // register to_initiator_0_taggedReg
  assign to_initiator_0_taggedReg$D_IN =
	     WILL_FIRE_RL_to_initiator_0_rule_enq ?
	       MUX_to_initiator_0_taggedReg$write_1__VAL_1 :
	       45'h0AAAAAAAAAAA ;
  assign to_initiator_0_taggedReg$EN =
	     WILL_FIRE_RL_to_initiator_0_rule_enq ||
	     EN_initiator_0_response_get ;

  // register to_initiator_1_round_robin
  assign to_initiator_1_round_robin$D_IN = !to_initiator_1_round_robin ;
  assign to_initiator_1_round_robin$EN =
	     WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // register to_initiator_1_taggedReg
  assign to_initiator_1_taggedReg$D_IN =
	     WILL_FIRE_RL_to_initiator_1_rule_enq ?
	       MUX_to_initiator_1_taggedReg$write_1__VAL_1 :
	       45'h0AAAAAAAAAAA ;
  assign to_initiator_1_taggedReg$EN =
	     WILL_FIRE_RL_to_initiator_1_rule_enq ||
	     EN_initiator_1_response_get ;

  // register to_target_0_round_robin
  assign to_target_0_round_robin$D_IN = !to_target_0_round_robin ;
  assign to_target_0_round_robin$EN =
	     WILL_FIRE_RL_both_initiators_to_target_0 ;

  // register to_target_0_taggedReg
  assign to_target_0_taggedReg$D_IN =
	     { to_target_0_rw_enq$whas, to_target_0_rw_enq$wget } ;
  assign to_target_0_taggedReg$EN =
	     WILL_FIRE_RL_to_target_0_rule_update_final ;

  // register to_target_1_round_robin
  assign to_target_1_round_robin$D_IN = !to_target_1_round_robin ;
  assign to_target_1_round_robin$EN =
	     WILL_FIRE_RL_both_initiators_to_target_1 ;

  // register to_target_1_taggedReg
  assign to_target_1_taggedReg$D_IN =
	     { to_target_1_rw_enq$whas, to_target_1_rw_enq$wget } ;
  assign to_target_1_taggedReg$EN =
	     WILL_FIRE_RL_to_target_1_rule_update_final ;

  // remaining internal signals
  assign IF_from_target_0_rw_enq_whas__8_THEN_NOT_from__ETC___d203 =
	     EN_target_0_response_put ?
	       !target_0_response_put[32] :
	       !from_target_0_taggedReg[32] ;
  assign IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205 =
	     EN_target_0_response_put ?
	       target_0_response_put[32] :
	       from_target_0_taggedReg[32] ;
  assign IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215 =
	     { EN_target_0_response_put ?
		 target_0_response_put[43] :
		 from_target_0_taggedReg[43],
	       IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d249 } ;
  assign IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d249 =
	     { EN_target_0_response_put ?
		 target_0_response_put[42:33] :
		 from_target_0_taggedReg[42:33],
	       IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d251 } ;
  assign IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d251 =
	     { IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205,
	       EN_target_0_response_put ?
		 target_0_response_put[31:0] :
		 from_target_0_taggedReg[31:0] } ;
  assign IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d204 =
	     EN_target_1_response_put ?
	       !target_1_response_put[32] :
	       !from_target_1_taggedReg[32] ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d206 =
	     EN_target_1_response_put ?
	       target_1_response_put[32] :
	       from_target_1_taggedReg[32] ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214 =
	     { EN_target_1_response_put ?
		 target_1_response_put[43] :
		 from_target_1_taggedReg[43],
	       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d248 } ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d248 =
	     { EN_target_1_response_put ?
		 target_1_response_put[42:33] :
		 from_target_1_taggedReg[42:33],
	       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d250 } ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d250 =
	     { IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d206,
	       EN_target_1_response_put ?
		 target_1_response_put[31:0] :
		 from_target_1_taggedReg[31:0] } ;
  assign IF_to_initiator_0_rw_enq_whas__50_THEN_to_init_ETC___d246 =
	     { to_initiator_0_rw_enq$whas ?
		 to_initiator_0_rw_enq$wget[42:33] :
		 to_initiator_0_taggedReg[42:33],
	       { to_initiator_0_rw_enq$whas ?
		   to_initiator_0_rw_enq$wget[32] :
		   to_initiator_0_taggedReg[32],
		 to_initiator_0_rw_enq$whas ?
		   to_initiator_0_rw_enq$wget[31:0] :
		   to_initiator_0_taggedReg[31:0] } } ;
  assign IF_to_initiator_1_rw_enq_whas__44_THEN_to_init_ETC___d244 =
	     { to_initiator_1_rw_enq$whas ?
		 _x__h664[42:33] :
		 to_initiator_1_taggedReg[42:33],
	       { to_initiator_1_rw_enq$whas ?
		   _x__h664[32] :
		   to_initiator_1_taggedReg[32],
		 to_initiator_1_rw_enq$whas ?
		   _x__h664[31:0] :
		   to_initiator_1_taggedReg[31:0] } } ;
  assign NOT_to_initiator_0_taggedReg_1_BIT_44_2_3_AND__ETC___d76 =
	     !to_initiator_0_taggedReg[44] &&
	     (from_target_0_taggedReg[44] || EN_target_0_response_put) &&
	     (IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d205 ||
	      from_target_1_taggedReg[44] ||
	      EN_target_1_response_put) &&
	     (to_initiator_0_round_robin || from_target_1_taggedReg[44] ||
	      EN_target_1_response_put) ;
  assign NOT_to_initiator_1_taggedReg_BIT_44_AND_from_t_ETC___d56 =
	     !to_initiator_1_taggedReg[44] &&
	     (from_target_0_taggedReg[44] || EN_target_0_response_put) &&
	     (IF_from_target_0_rw_enq_whas__8_THEN_NOT_from__ETC___d203 ||
	      from_target_1_taggedReg[44] ||
	      EN_target_1_response_put) &&
	     (to_initiator_1_round_robin || from_target_1_taggedReg[44] ||
	      EN_target_1_response_put) ;
  assign NOT_to_target_0_taggedReg_05_BIT_76_06_07_OR_t_ETC___d120 =
	     (!to_target_0_taggedReg[76] || EN_target_0_request_get) &&
	     (from_initiator_0_taggedReg[32] ||
	      from_initiator_1_taggedReg[76]) &&
	     (to_target_0_round_robin || from_initiator_1_taggedReg[76]) ;
  always@(WILL_FIRE_RL_both_targets_to_initiator_1 or
	  MUX_to_initiator_1_rw_enq$wset_1__VAL_1 or
	  WILL_FIRE_RL_target_0_to_initiator_1 or
	  IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215 or
	  WILL_FIRE_RL_target_1_to_initiator_1 or
	  IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_targets_to_initiator_1:
	  _x__h664 = MUX_to_initiator_1_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_target_0_to_initiator_1:
	  _x__h664 =
	      IF_from_target_0_rw_enq_whas__8_THEN_from_targ_ETC___d215;
      WILL_FIRE_RL_target_1_to_initiator_1:
	  _x__h664 =
	      IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d214;
      default: _x__h664 = 44'hAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        from_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	    77'h0AAAAAAAAAAAAAAAAAAA;
	from_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	    77'h0AAAAAAAAAAAAAAAAAAA;
	from_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
	from_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
	to_initiator_0_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
	to_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
	to_initiator_1_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
	to_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
	to_target_0_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
	to_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	    77'h0AAAAAAAAAAAAAAAAAAA;
	to_target_1_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
	to_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	    77'h0AAAAAAAAAAAAAAAAAAA;
      end
    else
      begin
        if (from_initiator_0_taggedReg$EN)
	  from_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      from_initiator_0_taggedReg$D_IN;
	if (from_initiator_1_taggedReg$EN)
	  from_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      from_initiator_1_taggedReg$D_IN;
	if (from_target_0_taggedReg$EN)
	  from_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      from_target_0_taggedReg$D_IN;
	if (from_target_1_taggedReg$EN)
	  from_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      from_target_1_taggedReg$D_IN;
	if (to_initiator_0_round_robin$EN)
	  to_initiator_0_round_robin <= `BSV_ASSIGNMENT_DELAY
	      to_initiator_0_round_robin$D_IN;
	if (to_initiator_0_taggedReg$EN)
	  to_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      to_initiator_0_taggedReg$D_IN;
	if (to_initiator_1_round_robin$EN)
	  to_initiator_1_round_robin <= `BSV_ASSIGNMENT_DELAY
	      to_initiator_1_round_robin$D_IN;
	if (to_initiator_1_taggedReg$EN)
	  to_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      to_initiator_1_taggedReg$D_IN;
	if (to_target_0_round_robin$EN)
	  to_target_0_round_robin <= `BSV_ASSIGNMENT_DELAY
	      to_target_0_round_robin$D_IN;
	if (to_target_0_taggedReg$EN)
	  to_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      to_target_0_taggedReg$D_IN;
	if (to_target_1_round_robin$EN)
	  to_target_1_round_robin <= `BSV_ASSIGNMENT_DELAY
	      to_target_1_round_robin$D_IN;
	if (to_target_1_taggedReg$EN)
	  to_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
	      to_target_1_taggedReg$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    from_initiator_0_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    from_initiator_1_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    from_target_0_taggedReg = 45'h0AAAAAAAAAAA;
    from_target_1_taggedReg = 45'h0AAAAAAAAAAA;
    to_initiator_0_round_robin = 1'h0;
    to_initiator_0_taggedReg = 45'h0AAAAAAAAAAA;
    to_initiator_1_round_robin = 1'h0;
    to_initiator_1_taggedReg = 45'h0AAAAAAAAAAA;
    to_target_0_round_robin = 1'h0;
    to_target_0_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    to_target_1_round_robin = 1'h0;
    to_target_1_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkSwitch

