//
// Generated by Bluespec Compiler, version 2006.11 (build 9629, 2006-11-11)
// 
// On Mon Feb 12 20:57:44 EST 2007
// 
// Method conflict info:
// (none)
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1
// RST_N                          I     1
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkTb(CLK,
	    RST_N);
  input  CLK;
  input  RST_N;

  // register initiator_0_rand32_r
  reg [31 : 0] initiator_0_rand32_r;
  wire [31 : 0] initiator_0_rand32_r$D_IN;
  wire initiator_0_rand32_r$EN;

  // register initiator_1_rand32_r
  reg [31 : 0] initiator_1_rand32_r;
  wire [31 : 0] initiator_1_rand32_r$D_IN;
  wire initiator_1_rand32_r$EN;

  // submodule initiator_0_expected_resps_0
  wire [43 : 0] initiator_0_expected_resps_0$D_IN,
		initiator_0_expected_resps_0$D_OUT;
  wire initiator_0_expected_resps_0$CLR,
       initiator_0_expected_resps_0$DEQ,
       initiator_0_expected_resps_0$EMPTY_N,
       initiator_0_expected_resps_0$ENQ,
       initiator_0_expected_resps_0$FULL_N;
  SizedFIFO #(.p1width(44),
	      .p2depth(10),
	      .p3cntr_width(4),
	      .guarded(1)) initiator_0_expected_resps_0(.RST_N(RST_N),
							.CLK(CLK),
							.D_IN(initiator_0_expected_resps_0$D_IN),
							.ENQ(initiator_0_expected_resps_0$ENQ),
							.DEQ(initiator_0_expected_resps_0$DEQ),
							.CLR(initiator_0_expected_resps_0$CLR),
							.D_OUT(initiator_0_expected_resps_0$D_OUT),
							.FULL_N(initiator_0_expected_resps_0$FULL_N),
							.EMPTY_N(initiator_0_expected_resps_0$EMPTY_N));

  // submodule initiator_0_expected_resps_1
  wire [43 : 0] initiator_0_expected_resps_1$D_IN,
		initiator_0_expected_resps_1$D_OUT;
  wire initiator_0_expected_resps_1$CLR,
       initiator_0_expected_resps_1$DEQ,
       initiator_0_expected_resps_1$EMPTY_N,
       initiator_0_expected_resps_1$ENQ,
       initiator_0_expected_resps_1$FULL_N;
  SizedFIFO #(.p1width(44),
	      .p2depth(10),
	      .p3cntr_width(4),
	      .guarded(1)) initiator_0_expected_resps_1(.RST_N(RST_N),
							.CLK(CLK),
							.D_IN(initiator_0_expected_resps_1$D_IN),
							.ENQ(initiator_0_expected_resps_1$ENQ),
							.DEQ(initiator_0_expected_resps_1$DEQ),
							.CLR(initiator_0_expected_resps_1$CLR),
							.D_OUT(initiator_0_expected_resps_1$D_OUT),
							.FULL_N(initiator_0_expected_resps_1$FULL_N),
							.EMPTY_N(initiator_0_expected_resps_1$EMPTY_N));

  // submodule initiator_0_reqs
  wire [75 : 0] initiator_0_reqs$D_IN, initiator_0_reqs$D_OUT;
  wire initiator_0_reqs$CLR,
       initiator_0_reqs$DEQ,
       initiator_0_reqs$EMPTY_N,
       initiator_0_reqs$ENQ,
       initiator_0_reqs$FULL_N;
  FIFO2 #(.width(76), .guarded(1)) initiator_0_reqs(.RST_N(RST_N),
						    .CLK(CLK),
						    .D_IN(initiator_0_reqs$D_IN),
						    .ENQ(initiator_0_reqs$ENQ),
						    .DEQ(initiator_0_reqs$DEQ),
						    .CLR(initiator_0_reqs$CLR),
						    .D_OUT(initiator_0_reqs$D_OUT),
						    .FULL_N(initiator_0_reqs$FULL_N),
						    .EMPTY_N(initiator_0_reqs$EMPTY_N));

  // submodule initiator_0_resps
  wire [43 : 0] initiator_0_resps$D_IN, initiator_0_resps$D_OUT;
  wire initiator_0_resps$CLR,
       initiator_0_resps$DEQ,
       initiator_0_resps$EMPTY_N,
       initiator_0_resps$ENQ,
       initiator_0_resps$FULL_N;
  FIFO2 #(.width(44), .guarded(1)) initiator_0_resps(.RST_N(RST_N),
						     .CLK(CLK),
						     .D_IN(initiator_0_resps$D_IN),
						     .ENQ(initiator_0_resps$ENQ),
						     .DEQ(initiator_0_resps$DEQ),
						     .CLR(initiator_0_resps$CLR),
						     .D_OUT(initiator_0_resps$D_OUT),
						     .FULL_N(initiator_0_resps$FULL_N),
						     .EMPTY_N(initiator_0_resps$EMPTY_N));

  // submodule initiator_1_expected_resps_0
  wire [43 : 0] initiator_1_expected_resps_0$D_IN,
		initiator_1_expected_resps_0$D_OUT;
  wire initiator_1_expected_resps_0$CLR,
       initiator_1_expected_resps_0$DEQ,
       initiator_1_expected_resps_0$EMPTY_N,
       initiator_1_expected_resps_0$ENQ,
       initiator_1_expected_resps_0$FULL_N;
  SizedFIFO #(.p1width(44),
	      .p2depth(10),
	      .p3cntr_width(4),
	      .guarded(1)) initiator_1_expected_resps_0(.RST_N(RST_N),
							.CLK(CLK),
							.D_IN(initiator_1_expected_resps_0$D_IN),
							.ENQ(initiator_1_expected_resps_0$ENQ),
							.DEQ(initiator_1_expected_resps_0$DEQ),
							.CLR(initiator_1_expected_resps_0$CLR),
							.D_OUT(initiator_1_expected_resps_0$D_OUT),
							.FULL_N(initiator_1_expected_resps_0$FULL_N),
							.EMPTY_N(initiator_1_expected_resps_0$EMPTY_N));

  // submodule initiator_1_expected_resps_1
  wire [43 : 0] initiator_1_expected_resps_1$D_IN,
		initiator_1_expected_resps_1$D_OUT;
  wire initiator_1_expected_resps_1$CLR,
       initiator_1_expected_resps_1$DEQ,
       initiator_1_expected_resps_1$EMPTY_N,
       initiator_1_expected_resps_1$ENQ,
       initiator_1_expected_resps_1$FULL_N;
  SizedFIFO #(.p1width(44),
	      .p2depth(10),
	      .p3cntr_width(4),
	      .guarded(1)) initiator_1_expected_resps_1(.RST_N(RST_N),
							.CLK(CLK),
							.D_IN(initiator_1_expected_resps_1$D_IN),
							.ENQ(initiator_1_expected_resps_1$ENQ),
							.DEQ(initiator_1_expected_resps_1$DEQ),
							.CLR(initiator_1_expected_resps_1$CLR),
							.D_OUT(initiator_1_expected_resps_1$D_OUT),
							.FULL_N(initiator_1_expected_resps_1$FULL_N),
							.EMPTY_N(initiator_1_expected_resps_1$EMPTY_N));

  // submodule initiator_1_reqs
  wire [75 : 0] initiator_1_reqs$D_IN, initiator_1_reqs$D_OUT;
  wire initiator_1_reqs$CLR,
       initiator_1_reqs$DEQ,
       initiator_1_reqs$EMPTY_N,
       initiator_1_reqs$ENQ,
       initiator_1_reqs$FULL_N;
  FIFO2 #(.width(76), .guarded(1)) initiator_1_reqs(.RST_N(RST_N),
						    .CLK(CLK),
						    .D_IN(initiator_1_reqs$D_IN),
						    .ENQ(initiator_1_reqs$ENQ),
						    .DEQ(initiator_1_reqs$DEQ),
						    .CLR(initiator_1_reqs$CLR),
						    .D_OUT(initiator_1_reqs$D_OUT),
						    .FULL_N(initiator_1_reqs$FULL_N),
						    .EMPTY_N(initiator_1_reqs$EMPTY_N));

  // submodule initiator_1_resps
  wire [43 : 0] initiator_1_resps$D_IN, initiator_1_resps$D_OUT;
  wire initiator_1_resps$CLR,
       initiator_1_resps$DEQ,
       initiator_1_resps$EMPTY_N,
       initiator_1_resps$ENQ,
       initiator_1_resps$FULL_N;
  FIFO2 #(.width(44), .guarded(1)) initiator_1_resps(.RST_N(RST_N),
						     .CLK(CLK),
						     .D_IN(initiator_1_resps$D_IN),
						     .ENQ(initiator_1_resps$ENQ),
						     .DEQ(initiator_1_resps$DEQ),
						     .CLR(initiator_1_resps$CLR),
						     .D_OUT(initiator_1_resps$D_OUT),
						     .FULL_N(initiator_1_resps$FULL_N),
						     .EMPTY_N(initiator_1_resps$EMPTY_N));

  // submodule target_0_reqs
  wire [75 : 0] target_0_reqs$D_IN, target_0_reqs$D_OUT;
  wire target_0_reqs$CLR,
       target_0_reqs$DEQ,
       target_0_reqs$EMPTY_N,
       target_0_reqs$ENQ,
       target_0_reqs$FULL_N;
  FIFO2 #(.width(76), .guarded(1)) target_0_reqs(.RST_N(RST_N),
						 .CLK(CLK),
						 .D_IN(target_0_reqs$D_IN),
						 .ENQ(target_0_reqs$ENQ),
						 .DEQ(target_0_reqs$DEQ),
						 .CLR(target_0_reqs$CLR),
						 .D_OUT(target_0_reqs$D_OUT),
						 .FULL_N(target_0_reqs$FULL_N),
						 .EMPTY_N(target_0_reqs$EMPTY_N));

  // submodule target_0_resps
  wire [43 : 0] target_0_resps$D_IN, target_0_resps$D_OUT;
  wire target_0_resps$CLR,
       target_0_resps$DEQ,
       target_0_resps$EMPTY_N,
       target_0_resps$ENQ,
       target_0_resps$FULL_N;
  FIFO2 #(.width(44), .guarded(1)) target_0_resps(.RST_N(RST_N),
						  .CLK(CLK),
						  .D_IN(target_0_resps$D_IN),
						  .ENQ(target_0_resps$ENQ),
						  .DEQ(target_0_resps$DEQ),
						  .CLR(target_0_resps$CLR),
						  .D_OUT(target_0_resps$D_OUT),
						  .FULL_N(target_0_resps$FULL_N),
						  .EMPTY_N(target_0_resps$EMPTY_N));

  // submodule target_1_reqs
  wire [75 : 0] target_1_reqs$D_IN, target_1_reqs$D_OUT;
  wire target_1_reqs$CLR,
       target_1_reqs$DEQ,
       target_1_reqs$EMPTY_N,
       target_1_reqs$ENQ,
       target_1_reqs$FULL_N;
  FIFO2 #(.width(76), .guarded(1)) target_1_reqs(.RST_N(RST_N),
						 .CLK(CLK),
						 .D_IN(target_1_reqs$D_IN),
						 .ENQ(target_1_reqs$ENQ),
						 .DEQ(target_1_reqs$DEQ),
						 .CLR(target_1_reqs$CLR),
						 .D_OUT(target_1_reqs$D_OUT),
						 .FULL_N(target_1_reqs$FULL_N),
						 .EMPTY_N(target_1_reqs$EMPTY_N));

  // submodule target_1_resps
  wire [43 : 0] target_1_resps$D_IN, target_1_resps$D_OUT;
  wire target_1_resps$CLR,
       target_1_resps$DEQ,
       target_1_resps$EMPTY_N,
       target_1_resps$ENQ,
       target_1_resps$FULL_N;
  FIFO2 #(.width(44), .guarded(1)) target_1_resps(.RST_N(RST_N),
						  .CLK(CLK),
						  .D_IN(target_1_resps$D_IN),
						  .ENQ(target_1_resps$ENQ),
						  .DEQ(target_1_resps$DEQ),
						  .CLR(target_1_resps$CLR),
						  .D_OUT(target_1_resps$D_OUT),
						  .FULL_N(target_1_resps$FULL_N),
						  .EMPTY_N(target_1_resps$EMPTY_N));

  // submodule the_switch
  wire [75 : 0] the_switch$initiator_0_request_put,
		the_switch$initiator_1_request_put,
		the_switch$target_0_request_get,
		the_switch$target_1_request_get;
  wire [43 : 0] the_switch$initiator_0_response_get,
		the_switch$initiator_1_response_get,
		the_switch$target_0_response_put,
		the_switch$target_1_response_put;
  wire the_switch$EN_initiator_0_request_put,
       the_switch$EN_initiator_0_response_get,
       the_switch$EN_initiator_1_request_put,
       the_switch$EN_initiator_1_response_get,
       the_switch$EN_target_0_request_get,
       the_switch$EN_target_0_response_put,
       the_switch$EN_target_1_request_get,
       the_switch$EN_target_1_response_put,
       the_switch$RDY_initiator_0_request_put,
       the_switch$RDY_initiator_0_response_get,
       the_switch$RDY_initiator_1_request_put,
       the_switch$RDY_initiator_1_response_get,
       the_switch$RDY_target_0_request_get,
       the_switch$RDY_target_0_response_put,
       the_switch$RDY_target_1_request_get,
       the_switch$RDY_target_1_response_put;
  mkSwitch the_switch(.CLK(CLK),
		      .RST_N(RST_N),
		      .initiator_0_request_put(the_switch$initiator_0_request_put),
		      .initiator_1_request_put(the_switch$initiator_1_request_put),
		      .target_0_response_put(the_switch$target_0_response_put),
		      .target_1_response_put(the_switch$target_1_response_put),
		      .EN_initiator_0_request_put(the_switch$EN_initiator_0_request_put),
		      .EN_initiator_0_response_get(the_switch$EN_initiator_0_response_get),
		      .EN_initiator_1_request_put(the_switch$EN_initiator_1_request_put),
		      .EN_initiator_1_response_get(the_switch$EN_initiator_1_response_get),
		      .EN_target_0_request_get(the_switch$EN_target_0_request_get),
		      .EN_target_0_response_put(the_switch$EN_target_0_response_put),
		      .EN_target_1_request_get(the_switch$EN_target_1_request_get),
		      .EN_target_1_response_put(the_switch$EN_target_1_response_put),
		      .RDY_initiator_0_request_put(the_switch$RDY_initiator_0_request_put),
		      .initiator_0_response_get(the_switch$initiator_0_response_get),
		      .RDY_initiator_0_response_get(the_switch$RDY_initiator_0_response_get),
		      .RDY_initiator_1_request_put(the_switch$RDY_initiator_1_request_put),
		      .initiator_1_response_get(the_switch$initiator_1_response_get),
		      .RDY_initiator_1_response_get(the_switch$RDY_initiator_1_response_get),
		      .target_0_request_get(the_switch$target_0_request_get),
		      .RDY_target_0_request_get(the_switch$RDY_target_0_request_get),
		      .RDY_target_0_response_put(the_switch$RDY_target_0_response_put),
		      .target_1_request_get(the_switch$target_1_request_get),
		      .RDY_target_1_request_get(the_switch$RDY_target_1_request_get),
		      .RDY_target_1_response_put(the_switch$RDY_target_1_response_put));

  // rule scheduling signals
  wire CAN_FIRE_RL_ClientServerRequest,
       CAN_FIRE_RL_ClientServerRequest_1,
       CAN_FIRE_RL_ClientServerRequest_2,
       CAN_FIRE_RL_ClientServerRequest_3,
       CAN_FIRE_RL_ClientServerResponse,
       CAN_FIRE_RL_ClientServerResponse_1,
       CAN_FIRE_RL_ClientServerResponse_2,
       CAN_FIRE_RL_ClientServerResponse_3,
       CAN_FIRE_RL_initiator_0_accept_resps_from_0,
       CAN_FIRE_RL_initiator_0_accept_resps_from_1,
       CAN_FIRE_RL_initiator_0_gen_reqs,
       CAN_FIRE_RL_initiator_1_accept_resps_from_0,
       CAN_FIRE_RL_initiator_1_accept_resps_from_1,
       CAN_FIRE_RL_initiator_1_gen_reqs,
       CAN_FIRE_RL_target_0_respond,
       CAN_FIRE_RL_target_1_respond,
       WILL_FIRE_RL_ClientServerRequest,
       WILL_FIRE_RL_ClientServerRequest_1,
       WILL_FIRE_RL_ClientServerRequest_2,
       WILL_FIRE_RL_ClientServerRequest_3,
       WILL_FIRE_RL_ClientServerResponse,
       WILL_FIRE_RL_ClientServerResponse_1,
       WILL_FIRE_RL_ClientServerResponse_2,
       WILL_FIRE_RL_ClientServerResponse_3,
       WILL_FIRE_RL_initiator_0_accept_resps_from_0,
       WILL_FIRE_RL_initiator_0_accept_resps_from_1,
       WILL_FIRE_RL_initiator_0_gen_reqs,
       WILL_FIRE_RL_initiator_1_accept_resps_from_0,
       WILL_FIRE_RL_initiator_1_accept_resps_from_1,
       WILL_FIRE_RL_initiator_1_gen_reqs,
       WILL_FIRE_RL_target_0_respond,
       WILL_FIRE_RL_target_1_respond;

  // remaining internal signals
  wire [31 : 0] req_reqAddr__h1415,
		req_reqAddr__h291,
		req_reqData__h1416,
		req_reqData__h292;
  wire [1 : 0] IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277,
	       IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278;
  wire NOT_IF_NOT_initiator_0_rand32_r_25_AND_7_26_UL_ETC___d237,
       NOT_IF_NOT_initiator_1_rand32_r_31_AND_7_32_UL_ETC___d143,
       NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217,
       NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192,
       NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123,
       NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98,
       initiator_0_expected_resps_0_first__02_BITS_31_ETC___d213,
       initiator_0_expected_resps_0_first__02_BITS_42_ETC___d207,
       initiator_0_expected_resps_0_first__02_BIT_32__ETC___d210,
       initiator_0_expected_resps_0_first__02_BIT_43__ETC___d204,
       initiator_0_expected_resps_1_first__77_BITS_31_ETC___d188,
       initiator_0_expected_resps_1_first__77_BITS_42_ETC___d182,
       initiator_0_expected_resps_1_first__77_BIT_32__ETC___d185,
       initiator_0_expected_resps_1_first__77_BIT_43__ETC___d179,
       initiator_1_expected_resps_0_first__08_BITS_31_ETC___d119,
       initiator_1_expected_resps_0_first__08_BITS_42_ETC___d113,
       initiator_1_expected_resps_0_first__08_BIT_32__ETC___d116,
       initiator_1_expected_resps_0_first__08_BIT_43__ETC___d110,
       initiator_1_expected_resps_1_first__3_BITS_31__ETC___d94,
       initiator_1_expected_resps_1_first__3_BITS_42__ETC___d88,
       initiator_1_expected_resps_1_first__3_BIT_32_0_ETC___d91,
       initiator_1_expected_resps_1_first__3_BIT_43_4_ETC___d85;

  // rule RL_ClientServerRequest_3
  assign WILL_FIRE_RL_ClientServerRequest_3 =
	     the_switch$RDY_target_1_request_get && target_1_reqs$FULL_N ;
  assign CAN_FIRE_RL_ClientServerRequest_3 =
	     WILL_FIRE_RL_ClientServerRequest_3 ;

  // rule RL_ClientServerResponse_3
  assign WILL_FIRE_RL_ClientServerResponse_3 =
	     the_switch$RDY_target_1_response_put && target_1_resps$EMPTY_N ;
  assign CAN_FIRE_RL_ClientServerResponse_3 =
	     WILL_FIRE_RL_ClientServerResponse_3 ;

  // rule RL_ClientServerRequest_2
  assign WILL_FIRE_RL_ClientServerRequest_2 =
	     the_switch$RDY_target_0_request_get && target_0_reqs$FULL_N ;
  assign CAN_FIRE_RL_ClientServerRequest_2 =
	     WILL_FIRE_RL_ClientServerRequest_2 ;

  // rule RL_ClientServerResponse_2
  assign WILL_FIRE_RL_ClientServerResponse_2 =
	     the_switch$RDY_target_0_response_put && target_0_resps$EMPTY_N ;
  assign CAN_FIRE_RL_ClientServerResponse_2 =
	     WILL_FIRE_RL_ClientServerResponse_2 ;

  // rule RL_ClientServerRequest_1
  assign WILL_FIRE_RL_ClientServerRequest_1 =
	     the_switch$RDY_initiator_1_request_put &&
	     initiator_1_reqs$EMPTY_N ;
  assign CAN_FIRE_RL_ClientServerRequest_1 =
	     WILL_FIRE_RL_ClientServerRequest_1 ;

  // rule RL_ClientServerResponse_1
  assign WILL_FIRE_RL_ClientServerResponse_1 =
	     the_switch$RDY_initiator_1_response_get &&
	     initiator_1_resps$FULL_N ;
  assign CAN_FIRE_RL_ClientServerResponse_1 =
	     WILL_FIRE_RL_ClientServerResponse_1 ;

  // rule RL_ClientServerRequest
  assign WILL_FIRE_RL_ClientServerRequest =
	     the_switch$RDY_initiator_0_request_put &&
	     initiator_0_reqs$EMPTY_N ;
  assign CAN_FIRE_RL_ClientServerRequest = WILL_FIRE_RL_ClientServerRequest ;

  // rule RL_ClientServerResponse
  assign WILL_FIRE_RL_ClientServerResponse =
	     the_switch$RDY_initiator_0_response_get &&
	     initiator_0_resps$FULL_N ;
  assign CAN_FIRE_RL_ClientServerResponse =
	     WILL_FIRE_RL_ClientServerResponse ;

  // rule RL_target_1_respond
  assign WILL_FIRE_RL_target_1_respond =
	     target_1_reqs$EMPTY_N &&
	     (target_1_reqs$D_OUT[75:74] != 2'd2 || target_1_resps$FULL_N) ;
  assign CAN_FIRE_RL_target_1_respond = WILL_FIRE_RL_target_1_respond ;

  // rule RL_target_0_respond
  assign WILL_FIRE_RL_target_0_respond =
	     target_0_reqs$EMPTY_N &&
	     (target_0_reqs$D_OUT[75:74] != 2'd2 || target_0_resps$FULL_N) ;
  assign CAN_FIRE_RL_target_0_respond = WILL_FIRE_RL_target_0_respond ;

  // rule RL_initiator_1_accept_resps_from_1
  assign WILL_FIRE_RL_initiator_1_accept_resps_from_1 =
	     initiator_1_resps$EMPTY_N &&
	     initiator_1_expected_resps_1$EMPTY_N &&
	     initiator_1_resps$D_OUT[42:33] != 10'd0 ;
  assign CAN_FIRE_RL_initiator_1_accept_resps_from_1 =
	     WILL_FIRE_RL_initiator_1_accept_resps_from_1 ;

  // rule RL_initiator_1_accept_resps_from_0
  assign WILL_FIRE_RL_initiator_1_accept_resps_from_0 =
	     initiator_1_resps$EMPTY_N &&
	     initiator_1_expected_resps_0$EMPTY_N &&
	     initiator_1_resps$D_OUT[42:33] == 10'd0 ;
  assign CAN_FIRE_RL_initiator_1_accept_resps_from_0 =
	     WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;

  // rule RL_initiator_1_gen_reqs
  assign WILL_FIRE_RL_initiator_1_gen_reqs =
	     initiator_1_reqs$FULL_N &&
	     NOT_IF_NOT_initiator_1_rand32_r_31_AND_7_32_UL_ETC___d143 ;
  assign CAN_FIRE_RL_initiator_1_gen_reqs =
	     WILL_FIRE_RL_initiator_1_gen_reqs ;

  // rule RL_initiator_0_accept_resps_from_1
  assign WILL_FIRE_RL_initiator_0_accept_resps_from_1 =
	     initiator_0_resps$EMPTY_N &&
	     initiator_0_expected_resps_1$EMPTY_N &&
	     initiator_0_resps$D_OUT[42:33] != 10'd0 ;
  assign CAN_FIRE_RL_initiator_0_accept_resps_from_1 =
	     WILL_FIRE_RL_initiator_0_accept_resps_from_1 ;

  // rule RL_initiator_0_accept_resps_from_0
  assign WILL_FIRE_RL_initiator_0_accept_resps_from_0 =
	     initiator_0_resps$EMPTY_N &&
	     initiator_0_expected_resps_0$EMPTY_N &&
	     initiator_0_resps$D_OUT[42:33] == 10'd0 ;
  assign CAN_FIRE_RL_initiator_0_accept_resps_from_0 =
	     WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;

  // rule RL_initiator_0_gen_reqs
  assign WILL_FIRE_RL_initiator_0_gen_reqs =
	     initiator_0_reqs$FULL_N &&
	     NOT_IF_NOT_initiator_0_rand32_r_25_AND_7_26_UL_ETC___d237 ;
  assign CAN_FIRE_RL_initiator_0_gen_reqs =
	     WILL_FIRE_RL_initiator_0_gen_reqs ;

  // register initiator_0_rand32_r
  assign initiator_0_rand32_r$D_IN =
	     initiator_0_rand32_r[0] ?
	       { 1'd0, initiator_0_rand32_r[31:1] } ^ 32'h80000057 :
	       { 1'd0, initiator_0_rand32_r[31:1] } ;
  assign initiator_0_rand32_r$EN = WILL_FIRE_RL_initiator_0_gen_reqs ;

  // register initiator_1_rand32_r
  assign initiator_1_rand32_r$D_IN =
	     initiator_1_rand32_r[0] ?
	       { 1'd0, initiator_1_rand32_r[31:1] } ^ 32'h80000062 :
	       { 1'd0, initiator_1_rand32_r[31:1] } ;
  assign initiator_1_rand32_r$EN = WILL_FIRE_RL_initiator_1_gen_reqs ;

  // submodule initiator_0_expected_resps_0
  assign initiator_0_expected_resps_0$D_IN =
	     { 28'd134217728, initiator_0_rand32_r[31:16] } ;
  assign initiator_0_expected_resps_0$DEQ =
	     WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;
  assign initiator_0_expected_resps_0$ENQ =
	     WILL_FIRE_RL_initiator_0_gen_reqs &&
	     IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 ==
	     2'd2 &&
	     !initiator_0_rand32_r[4] ;
  assign initiator_0_expected_resps_0$CLR = 1'b0 ;

  // submodule initiator_0_expected_resps_1
  assign initiator_0_expected_resps_1$D_IN =
	     { 28'd134348800, initiator_0_rand32_r[31:16] } ;
  assign initiator_0_expected_resps_1$DEQ =
	     WILL_FIRE_RL_initiator_0_accept_resps_from_1 ;
  assign initiator_0_expected_resps_1$ENQ =
	     WILL_FIRE_RL_initiator_0_gen_reqs &&
	     IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 ==
	     2'd2 &&
	     initiator_0_rand32_r[4] ;
  assign initiator_0_expected_resps_1$CLR = 1'b0 ;

  // submodule initiator_0_reqs
  assign initiator_0_reqs$D_IN =
	     { IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277,
	       10'd0,
	       req_reqAddr__h291,
	       req_reqData__h292 } ;
  assign initiator_0_reqs$DEQ = WILL_FIRE_RL_ClientServerRequest ;
  assign initiator_0_reqs$ENQ = WILL_FIRE_RL_initiator_0_gen_reqs ;
  assign initiator_0_reqs$CLR = 1'b0 ;

  // submodule initiator_0_resps
  assign initiator_0_resps$D_IN = the_switch$initiator_0_response_get ;
  assign initiator_0_resps$DEQ =
	     WILL_FIRE_RL_initiator_0_accept_resps_from_1 ||
	     WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;
  assign initiator_0_resps$ENQ = WILL_FIRE_RL_ClientServerResponse ;
  assign initiator_0_resps$CLR = 1'b0 ;

  // submodule initiator_1_expected_resps_0
  assign initiator_1_expected_resps_0$D_IN =
	     { 28'd134283264, initiator_1_rand32_r[31:16] } ;
  assign initiator_1_expected_resps_0$DEQ =
	     WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;
  assign initiator_1_expected_resps_0$ENQ =
	     WILL_FIRE_RL_initiator_1_gen_reqs &&
	     IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 ==
	     2'd2 &&
	     !initiator_1_rand32_r[4] ;
  assign initiator_1_expected_resps_0$CLR = 1'b0 ;

  // submodule initiator_1_expected_resps_1
  assign initiator_1_expected_resps_1$D_IN =
	     { 28'd134414336, initiator_1_rand32_r[31:16] } ;
  assign initiator_1_expected_resps_1$DEQ =
	     WILL_FIRE_RL_initiator_1_accept_resps_from_1 ;
  assign initiator_1_expected_resps_1$ENQ =
	     WILL_FIRE_RL_initiator_1_gen_reqs &&
	     IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 ==
	     2'd2 &&
	     initiator_1_rand32_r[4] ;
  assign initiator_1_expected_resps_1$CLR = 1'b0 ;

  // submodule initiator_1_reqs
  assign initiator_1_reqs$D_IN =
	     { IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278,
	       10'd1,
	       req_reqAddr__h1415,
	       req_reqData__h1416 } ;
  assign initiator_1_reqs$DEQ = WILL_FIRE_RL_ClientServerRequest_1 ;
  assign initiator_1_reqs$ENQ = WILL_FIRE_RL_initiator_1_gen_reqs ;
  assign initiator_1_reqs$CLR = 1'b0 ;

  // submodule initiator_1_resps
  assign initiator_1_resps$D_IN = the_switch$initiator_1_response_get ;
  assign initiator_1_resps$DEQ =
	     WILL_FIRE_RL_initiator_1_accept_resps_from_1 ||
	     WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;
  assign initiator_1_resps$ENQ = WILL_FIRE_RL_ClientServerResponse_1 ;
  assign initiator_1_resps$CLR = 1'b0 ;

  // submodule target_0_reqs
  assign target_0_reqs$D_IN = the_switch$target_0_request_get ;
  assign target_0_reqs$DEQ = WILL_FIRE_RL_target_0_respond ;
  assign target_0_reqs$ENQ = WILL_FIRE_RL_ClientServerRequest_2 ;
  assign target_0_reqs$CLR = 1'b0 ;

  // submodule target_0_resps
  assign target_0_resps$D_IN =
	     { 11'd1024,
	       target_0_reqs$D_OUT[64],
	       target_0_reqs$D_OUT[31:0] } ;
  assign target_0_resps$DEQ = WILL_FIRE_RL_ClientServerResponse_2 ;
  assign target_0_resps$ENQ =
	     WILL_FIRE_RL_target_0_respond &&
	     target_0_reqs$D_OUT[75:74] == 2'd2 ;
  assign target_0_resps$CLR = 1'b0 ;

  // submodule target_1_reqs
  assign target_1_reqs$D_IN = the_switch$target_1_request_get ;
  assign target_1_reqs$DEQ = WILL_FIRE_RL_target_1_respond ;
  assign target_1_reqs$ENQ = WILL_FIRE_RL_ClientServerRequest_3 ;
  assign target_1_reqs$CLR = 1'b0 ;

  // submodule target_1_resps
  assign target_1_resps$D_IN =
	     { 11'd1025,
	       target_1_reqs$D_OUT[64],
	       target_1_reqs$D_OUT[31:0] } ;
  assign target_1_resps$DEQ = WILL_FIRE_RL_ClientServerResponse_3 ;
  assign target_1_resps$ENQ =
	     WILL_FIRE_RL_target_1_respond &&
	     target_1_reqs$D_OUT[75:74] == 2'd2 ;
  assign target_1_resps$CLR = 1'b0 ;

  // submodule the_switch
  assign the_switch$initiator_0_request_put = initiator_0_reqs$D_OUT ;
  assign the_switch$initiator_1_request_put = initiator_1_reqs$D_OUT ;
  assign the_switch$target_0_response_put = target_0_resps$D_OUT ;
  assign the_switch$target_1_response_put = target_1_resps$D_OUT ;
  assign the_switch$EN_initiator_0_request_put =
	     WILL_FIRE_RL_ClientServerRequest ;
  assign the_switch$EN_initiator_0_response_get =
	     WILL_FIRE_RL_ClientServerResponse ;
  assign the_switch$EN_initiator_1_request_put =
	     WILL_FIRE_RL_ClientServerRequest_1 ;
  assign the_switch$EN_initiator_1_response_get =
	     WILL_FIRE_RL_ClientServerResponse_1 ;
  assign the_switch$EN_target_0_request_get =
	     WILL_FIRE_RL_ClientServerRequest_2 ;
  assign the_switch$EN_target_0_response_put =
	     WILL_FIRE_RL_ClientServerResponse_2 ;
  assign the_switch$EN_target_1_request_get =
	     WILL_FIRE_RL_ClientServerRequest_3 ;
  assign the_switch$EN_target_1_response_put =
	     WILL_FIRE_RL_ClientServerResponse_3 ;

  // remaining internal signals
  assign IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 =
	     ((initiator_0_rand32_r & 32'd7) <= 32'd5) ? 2'd2 : 2'd1 ;
  assign IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 =
	     ((initiator_1_rand32_r & 32'd7) <= 32'd5) ? 2'd2 : 2'd1 ;
  assign NOT_IF_NOT_initiator_0_rand32_r_25_AND_7_26_UL_ETC___d237 =
	     IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 !=
	     2'd2 ||
	     (initiator_0_rand32_r[4] ?
		initiator_0_expected_resps_1$FULL_N :
		initiator_0_expected_resps_0$FULL_N) ;
  assign NOT_IF_NOT_initiator_1_rand32_r_31_AND_7_32_UL_ETC___d143 =
	     IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 !=
	     2'd2 ||
	     (initiator_1_rand32_r[4] ?
		initiator_1_expected_resps_1$FULL_N :
		initiator_1_expected_resps_0$FULL_N) ;
  assign NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217 =
	     !initiator_0_expected_resps_0_first__02_BIT_43__ETC___d204 ||
	     !initiator_0_expected_resps_0_first__02_BITS_42_ETC___d207 ||
	     !initiator_0_expected_resps_0_first__02_BIT_32__ETC___d210 ||
	     !initiator_0_expected_resps_0_first__02_BITS_31_ETC___d213 ;
  assign NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192 =
	     !initiator_0_expected_resps_1_first__77_BIT_43__ETC___d179 ||
	     !initiator_0_expected_resps_1_first__77_BITS_42_ETC___d182 ||
	     !initiator_0_expected_resps_1_first__77_BIT_32__ETC___d185 ||
	     !initiator_0_expected_resps_1_first__77_BITS_31_ETC___d188 ;
  assign NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123 =
	     !initiator_1_expected_resps_0_first__08_BIT_43__ETC___d110 ||
	     !initiator_1_expected_resps_0_first__08_BITS_42_ETC___d113 ||
	     !initiator_1_expected_resps_0_first__08_BIT_32__ETC___d116 ||
	     !initiator_1_expected_resps_0_first__08_BITS_31_ETC___d119 ;
  assign NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98 =
	     !initiator_1_expected_resps_1_first__3_BIT_43_4_ETC___d85 ||
	     !initiator_1_expected_resps_1_first__3_BITS_42__ETC___d88 ||
	     !initiator_1_expected_resps_1_first__3_BIT_32_0_ETC___d91 ||
	     !initiator_1_expected_resps_1_first__3_BITS_31__ETC___d94 ;
  assign initiator_0_expected_resps_0_first__02_BITS_31_ETC___d213 =
	     initiator_0_expected_resps_0$D_OUT[31:0] ==
	     initiator_0_resps$D_OUT[31:0] ;
  assign initiator_0_expected_resps_0_first__02_BITS_42_ETC___d207 =
	     initiator_0_expected_resps_0$D_OUT[42:33] ==
	     initiator_0_resps$D_OUT[42:33] ;
  assign initiator_0_expected_resps_0_first__02_BIT_32__ETC___d210 =
	     initiator_0_expected_resps_0$D_OUT[32] ==
	     initiator_0_resps$D_OUT[32] ;
  assign initiator_0_expected_resps_0_first__02_BIT_43__ETC___d204 =
	     initiator_0_expected_resps_0$D_OUT[43] ==
	     initiator_0_resps$D_OUT[43] ;
  assign initiator_0_expected_resps_1_first__77_BITS_31_ETC___d188 =
	     initiator_0_expected_resps_1$D_OUT[31:0] ==
	     initiator_0_resps$D_OUT[31:0] ;
  assign initiator_0_expected_resps_1_first__77_BITS_42_ETC___d182 =
	     initiator_0_expected_resps_1$D_OUT[42:33] ==
	     initiator_0_resps$D_OUT[42:33] ;
  assign initiator_0_expected_resps_1_first__77_BIT_32__ETC___d185 =
	     initiator_0_expected_resps_1$D_OUT[32] ==
	     initiator_0_resps$D_OUT[32] ;
  assign initiator_0_expected_resps_1_first__77_BIT_43__ETC___d179 =
	     initiator_0_expected_resps_1$D_OUT[43] ==
	     initiator_0_resps$D_OUT[43] ;
  assign initiator_1_expected_resps_0_first__08_BITS_31_ETC___d119 =
	     initiator_1_expected_resps_0$D_OUT[31:0] ==
	     initiator_1_resps$D_OUT[31:0] ;
  assign initiator_1_expected_resps_0_first__08_BITS_42_ETC___d113 =
	     initiator_1_expected_resps_0$D_OUT[42:33] ==
	     initiator_1_resps$D_OUT[42:33] ;
  assign initiator_1_expected_resps_0_first__08_BIT_32__ETC___d116 =
	     initiator_1_expected_resps_0$D_OUT[32] ==
	     initiator_1_resps$D_OUT[32] ;
  assign initiator_1_expected_resps_0_first__08_BIT_43__ETC___d110 =
	     initiator_1_expected_resps_0$D_OUT[43] ==
	     initiator_1_resps$D_OUT[43] ;
  assign initiator_1_expected_resps_1_first__3_BITS_31__ETC___d94 =
	     initiator_1_expected_resps_1$D_OUT[31:0] ==
	     initiator_1_resps$D_OUT[31:0] ;
  assign initiator_1_expected_resps_1_first__3_BITS_42__ETC___d88 =
	     initiator_1_expected_resps_1$D_OUT[42:33] ==
	     initiator_1_resps$D_OUT[42:33] ;
  assign initiator_1_expected_resps_1_first__3_BIT_32_0_ETC___d91 =
	     initiator_1_expected_resps_1$D_OUT[32] ==
	     initiator_1_resps$D_OUT[32] ;
  assign initiator_1_expected_resps_1_first__3_BIT_43_4_ETC___d85 =
	     initiator_1_expected_resps_1$D_OUT[43] ==
	     initiator_1_resps$D_OUT[43] ;
  assign req_reqAddr__h1415 = { 20'd0, initiator_1_rand32_r[15:4] } ;
  assign req_reqAddr__h291 = { 20'd0, initiator_0_rand32_r[15:4] } ;
  assign req_reqData__h1416 = { 16'd0, initiator_1_rand32_r[31:16] } ;
  assign req_reqData__h292 = { 16'd0, initiator_0_rand32_r[31:16] } ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        initiator_0_rand32_r <= `BSV_ASSIGNMENT_DELAY 32'd1;
	initiator_1_rand32_r <= `BSV_ASSIGNMENT_DELAY 32'd1;
      end
    else
      begin
        if (initiator_0_rand32_r$EN)
	  initiator_0_rand32_r <= `BSV_ASSIGNMENT_DELAY
	      initiator_0_rand32_r$D_IN;
	if (initiator_1_rand32_r$EN)
	  initiator_1_rand32_r <= `BSV_ASSIGNMENT_DELAY
	      initiator_1_rand32_r$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    initiator_0_rand32_r = 32'hAAAAAAAA;
    initiator_1_rand32_r = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks
  
  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond)
	$write("Tb: target %d received request ", $signed(32'd1));
    if (RST_N) if (WILL_FIRE_RL_target_1_respond) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd0)
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd1)
	$write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
	  target_1_reqs$D_OUT[75:74] != 2'd0 &&
	  target_1_reqs$D_OUT[75:74] != 2'd1)
	$write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] != 2'd0)
	$write(", %h, %h, %h}",
	       target_1_reqs$D_OUT[73:64],
	       target_1_reqs$D_OUT[63:32],
	       target_1_reqs$D_OUT[31:0]);
    if (RST_N) if (WILL_FIRE_RL_target_1_respond) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd2)
	$write("              Sent response ");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd2)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd2)
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd2)
	$write(", %h, %h, %h",
	       10'd1,
	       target_1_reqs$D_OUT[64],
	       target_1_reqs$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond && target_1_reqs$D_OUT[75:74] == 2'd2)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond)
	$write("Tb: target %d received request ", $signed(32'd0));
    if (RST_N) if (WILL_FIRE_RL_target_0_respond) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd0)
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd1)
	$write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
	  target_0_reqs$D_OUT[75:74] != 2'd0 &&
	  target_0_reqs$D_OUT[75:74] != 2'd1)
	$write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] != 2'd0)
	$write(", %h, %h, %h}",
	       target_0_reqs$D_OUT[73:64],
	       target_0_reqs$D_OUT[63:32],
	       target_0_reqs$D_OUT[31:0]);
    if (RST_N) if (WILL_FIRE_RL_target_0_respond) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd2)
	$write("              Sent response ");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd2)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd2)
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd2)
	$write(", %h, %h, %h",
	       10'd0,
	       target_0_reqs$D_OUT[64],
	       target_0_reqs$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond && target_0_reqs$D_OUT[75:74] == 2'd2)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1)
	$write("Tb: initiator %d received response ", $signed(32'd1));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  !initiator_1_resps$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  initiator_1_resps$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  initiator_1_resps$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_1_resps$D_OUT[42:33],
	       initiator_1_resps$D_OUT[32],
	       initiator_1_resps$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98)
	$write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98 &&
	  !initiator_1_expected_resps_1$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98 &&
	  initiator_1_expected_resps_1$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98 &&
	  initiator_1_expected_resps_1$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_1_expected_resps_1$D_OUT[42:33],
	       initiator_1_expected_resps_1$D_OUT[32],
	       initiator_1_expected_resps_1$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  NOT_initiator_1_expected_resps_1_first__3_BIT__ETC___d98)
	$finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
	  initiator_1_expected_resps_1_first__3_BIT_43_4_ETC___d85 &&
	  initiator_1_expected_resps_1_first__3_BITS_42__ETC___d88 &&
	  initiator_1_expected_resps_1_first__3_BIT_32_0_ETC___d91 &&
	  initiator_1_expected_resps_1_first__3_BITS_31__ETC___d94)
	$display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0)
	$write("Tb: initiator %d received response ", $signed(32'd1));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  !initiator_1_resps$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  initiator_1_resps$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  initiator_1_resps$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_1_resps$D_OUT[42:33],
	       initiator_1_resps$D_OUT[32],
	       initiator_1_resps$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123)
	$write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123 &&
	  !initiator_1_expected_resps_0$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123 &&
	  initiator_1_expected_resps_0$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123 &&
	  initiator_1_expected_resps_0$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_1_expected_resps_0$D_OUT[42:33],
	       initiator_1_expected_resps_0$D_OUT[32],
	       initiator_1_expected_resps_0$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  NOT_initiator_1_expected_resps_0_first__08_BIT_ETC___d123)
	$finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
	  initiator_1_expected_resps_0_first__08_BIT_43__ETC___d110 &&
	  initiator_1_expected_resps_0_first__08_BITS_42_ETC___d113 &&
	  initiator_1_expected_resps_0_first__08_BIT_32__ETC___d116 &&
	  initiator_1_expected_resps_0_first__08_BITS_31_ETC___d119)
	$display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs)
	$write("Tb: initiator %d sent request ", $signed(32'd1));
    if (RST_N) if (WILL_FIRE_RL_initiator_1_gen_reqs) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
	  IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 == 2'd0)
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
	  IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 == 2'd1)
	$write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
	  IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 != 2'd0 &&
	  IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 != 2'd1)
	$write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
	  IF_NOT_initiator_1_rand32_r_31_AND_7_32_ULE_5__ETC___d278 != 2'd0)
	$write(", %h, %h, %h}",
	       10'd1,
	       req_reqAddr__h1415,
	       req_reqData__h1416);
    if (RST_N) if (WILL_FIRE_RL_initiator_1_gen_reqs) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1)
	$write("Tb: initiator %d received response ", $signed(32'd0));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  !initiator_0_resps$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  initiator_0_resps$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  initiator_0_resps$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_0_resps$D_OUT[42:33],
	       initiator_0_resps$D_OUT[32],
	       initiator_0_resps$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192)
	$write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192 &&
	  !initiator_0_expected_resps_1$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192 &&
	  initiator_0_expected_resps_1$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192 &&
	  initiator_0_expected_resps_1$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_0_expected_resps_1$D_OUT[42:33],
	       initiator_0_expected_resps_1$D_OUT[32],
	       initiator_0_expected_resps_1$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  NOT_initiator_0_expected_resps_1_first__77_BIT_ETC___d192)
	$finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
	  initiator_0_expected_resps_1_first__77_BIT_43__ETC___d179 &&
	  initiator_0_expected_resps_1_first__77_BITS_42_ETC___d182 &&
	  initiator_0_expected_resps_1_first__77_BIT_32__ETC___d185 &&
	  initiator_0_expected_resps_1_first__77_BITS_31_ETC___d188)
	$display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0)
	$write("Tb: initiator %d received response ", $signed(32'd0));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  !initiator_0_resps$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  initiator_0_resps$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  initiator_0_resps$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_0_resps$D_OUT[42:33],
	       initiator_0_resps$D_OUT[32],
	       initiator_0_resps$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217)
	$write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217)
	$write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217 &&
	  !initiator_0_expected_resps_0$D_OUT[43])
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217 &&
	  initiator_0_expected_resps_0$D_OUT[43])
	$write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217 &&
	  initiator_0_expected_resps_0$D_OUT[43])
	$write(", %h, %h, %h",
	       initiator_0_expected_resps_0$D_OUT[42:33],
	       initiator_0_expected_resps_0$D_OUT[32],
	       initiator_0_expected_resps_0$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217)
	$display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  NOT_initiator_0_expected_resps_0_first__02_BIT_ETC___d217)
	$finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
	  initiator_0_expected_resps_0_first__02_BIT_43__ETC___d204 &&
	  initiator_0_expected_resps_0_first__02_BITS_42_ETC___d207 &&
	  initiator_0_expected_resps_0_first__02_BIT_32__ETC___d210 &&
	  initiator_0_expected_resps_0_first__02_BITS_31_ETC___d213)
	$display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs)
	$write("Tb: initiator %d sent request ", $signed(32'd0));
    if (RST_N) if (WILL_FIRE_RL_initiator_0_gen_reqs) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
	  IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 == 2'd0)
	$write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
	  IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 == 2'd1)
	$write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
	  IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 != 2'd0 &&
	  IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 != 2'd1)
	$write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
	  IF_NOT_initiator_0_rand32_r_25_AND_7_26_ULE_5__ETC___d277 != 2'd0)
	$write(", %h, %h, %h}", 10'd0, req_reqAddr__h291, req_reqData__h292);
    if (RST_N) if (WILL_FIRE_RL_initiator_0_gen_reqs) $display("}");
  end
  // synopsys translate_on
endmodule  // mkTb

