//
// Generated by Bluespec Compiler, version 2006.11 (build 9629, 2006-11-11)
// 
// On Mon Feb 12 16:34:17 EST 2007
// 
// Method conflict info:
// (none)
// 
// Ports:
// Name                         I/O  size props
// CLK                            I     1
// RST_N                          I     1
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkTb(CLK,
            RST_N);
  input  CLK;
  input  RST_N;

  // inlined wires
  wire [75 : 0] initiator_0_reqs_rw_enq$wget, initiator_1_reqs_rw_enq$wget;
  wire [43 : 0] target_0_resps_rw_enq$wget, target_1_resps_rw_enq$wget;
  wire initiator_0_reqs_pw_deq$whas,
       initiator_0_resps_pw_deq$whas,
       initiator_0_resps_rw_enq$whas,
       initiator_1_reqs_pw_deq$whas,
       initiator_1_resps_pw_deq$whas,
       initiator_1_resps_rw_enq$whas,
       target_0_reqs_rw_enq$whas,
       target_0_resps_pw_deq$whas,
       target_0_resps_rw_enq$whas,
       target_1_reqs_rw_enq$whas,
       target_1_resps_pw_deq$whas,
       target_1_resps_rw_enq$whas;

  // register initiator_0_rand32_r
  reg [31 : 0] initiator_0_rand32_r;
  wire [31 : 0] initiator_0_rand32_r$D_IN;
  wire initiator_0_rand32_r$EN;

  // register initiator_0_reqs_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] initiator_0_reqs_taggedReg;
  wire [76 : 0] initiator_0_reqs_taggedReg$D_IN;
  wire initiator_0_reqs_taggedReg$EN;

  // register initiator_0_resps_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] initiator_0_resps_taggedReg;
  wire [44 : 0] initiator_0_resps_taggedReg$D_IN;
  wire initiator_0_resps_taggedReg$EN;

  // register initiator_1_rand32_r
  reg [31 : 0] initiator_1_rand32_r;
  wire [31 : 0] initiator_1_rand32_r$D_IN;
  wire initiator_1_rand32_r$EN;

  // register initiator_1_reqs_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] initiator_1_reqs_taggedReg;
  wire [76 : 0] initiator_1_reqs_taggedReg$D_IN;
  wire initiator_1_reqs_taggedReg$EN;

  // register initiator_1_resps_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] initiator_1_resps_taggedReg;
  wire [44 : 0] initiator_1_resps_taggedReg$D_IN;
  wire initiator_1_resps_taggedReg$EN;

  // register target_0_reqs_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] target_0_reqs_taggedReg;
  wire [76 : 0] target_0_reqs_taggedReg$D_IN;
  wire target_0_reqs_taggedReg$EN;

  // register target_0_resps_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] target_0_resps_taggedReg;
  wire [44 : 0] target_0_resps_taggedReg$D_IN;
  wire target_0_resps_taggedReg$EN;

  // register target_1_reqs_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] target_1_reqs_taggedReg;
  wire [76 : 0] target_1_reqs_taggedReg$D_IN;
  wire target_1_reqs_taggedReg$EN;

  // register target_1_resps_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] target_1_resps_taggedReg;
  wire [44 : 0] target_1_resps_taggedReg$D_IN;
  wire target_1_resps_taggedReg$EN;

  // submodule initiator_0_expected_resps_0
  wire [43 : 0] initiator_0_expected_resps_0$D_IN,
                initiator_0_expected_resps_0$D_OUT;
  wire initiator_0_expected_resps_0$CLR,
       initiator_0_expected_resps_0$DEQ,
       initiator_0_expected_resps_0$EMPTY_N,
       initiator_0_expected_resps_0$ENQ,
       initiator_0_expected_resps_0$FULL_N;
  SizedFIFO #(.p1width(44),
              .p2depth(10),
              .p3cntr_width(4),
              .guarded(1)) initiator_0_expected_resps_0(.RST_N(RST_N),
                                                        .CLK(CLK),
                                                        .D_IN(initiator_0_expected_resps_0$D_IN),
                                                        .ENQ(initiator_0_expected_resps_0$ENQ),
                                                        .DEQ(initiator_0_expected_resps_0$DEQ),
                                                        .CLR(initiator_0_expected_resps_0$CLR),
                                                        .D_OUT(initiator_0_expected_resps_0$D_OUT),
                                                        .FULL_N(initiator_0_expected_resps_0$FULL_N),
                                                        .EMPTY_N(initiator_0_expected_resps_0$EMPTY_N));

  // submodule initiator_0_expected_resps_1
  wire [43 : 0] initiator_0_expected_resps_1$D_IN,
                initiator_0_expected_resps_1$D_OUT;
  wire initiator_0_expected_resps_1$CLR,
       initiator_0_expected_resps_1$DEQ,
       initiator_0_expected_resps_1$EMPTY_N,
       initiator_0_expected_resps_1$ENQ,
       initiator_0_expected_resps_1$FULL_N;
  SizedFIFO #(.p1width(44),
              .p2depth(10),
              .p3cntr_width(4),
              .guarded(1)) initiator_0_expected_resps_1(.RST_N(RST_N),
                                                        .CLK(CLK),
                                                        .D_IN(initiator_0_expected_resps_1$D_IN),
                                                        .ENQ(initiator_0_expected_resps_1$ENQ),
                                                        .DEQ(initiator_0_expected_resps_1$DEQ),
                                                        .CLR(initiator_0_expected_resps_1$CLR),
                                                        .D_OUT(initiator_0_expected_resps_1$D_OUT),
                                                        .FULL_N(initiator_0_expected_resps_1$FULL_N),
                                                        .EMPTY_N(initiator_0_expected_resps_1$EMPTY_N));

  // submodule initiator_1_expected_resps_0
  wire [43 : 0] initiator_1_expected_resps_0$D_IN,
                initiator_1_expected_resps_0$D_OUT;
  wire initiator_1_expected_resps_0$CLR,
       initiator_1_expected_resps_0$DEQ,
       initiator_1_expected_resps_0$EMPTY_N,
       initiator_1_expected_resps_0$ENQ,
       initiator_1_expected_resps_0$FULL_N;
  SizedFIFO #(.p1width(44),
              .p2depth(10),
              .p3cntr_width(4),
              .guarded(1)) initiator_1_expected_resps_0(.RST_N(RST_N),
                                                        .CLK(CLK),
                                                        .D_IN(initiator_1_expected_resps_0$D_IN),
                                                        .ENQ(initiator_1_expected_resps_0$ENQ),
                                                        .DEQ(initiator_1_expected_resps_0$DEQ),
                                                        .CLR(initiator_1_expected_resps_0$CLR),
                                                        .D_OUT(initiator_1_expected_resps_0$D_OUT),
                                                        .FULL_N(initiator_1_expected_resps_0$FULL_N),
                                                        .EMPTY_N(initiator_1_expected_resps_0$EMPTY_N));

  // submodule initiator_1_expected_resps_1
  wire [43 : 0] initiator_1_expected_resps_1$D_IN,
                initiator_1_expected_resps_1$D_OUT;
  wire initiator_1_expected_resps_1$CLR,
       initiator_1_expected_resps_1$DEQ,
       initiator_1_expected_resps_1$EMPTY_N,
       initiator_1_expected_resps_1$ENQ,
       initiator_1_expected_resps_1$FULL_N;
  SizedFIFO #(.p1width(44),
              .p2depth(10),
              .p3cntr_width(4),
              .guarded(1)) initiator_1_expected_resps_1(.RST_N(RST_N),
                                                        .CLK(CLK),
                                                        .D_IN(initiator_1_expected_resps_1$D_IN),
                                                        .ENQ(initiator_1_expected_resps_1$ENQ),
                                                        .DEQ(initiator_1_expected_resps_1$DEQ),
                                                        .CLR(initiator_1_expected_resps_1$CLR),
                                                        .D_OUT(initiator_1_expected_resps_1$D_OUT),
                                                        .FULL_N(initiator_1_expected_resps_1$FULL_N),
                                                        .EMPTY_N(initiator_1_expected_resps_1$EMPTY_N));

  // submodule the_switch
  wire [75 : 0] the_switch$initiator_0_slave_req_putReq_req,
                the_switch$initiator_1_slave_req_putReq_req,
                the_switch$target_0_master_req_getReq,
                the_switch$target_1_master_req_getReq;
  wire [43 : 0] the_switch$initiator_0_slave_resp_getResp,
                the_switch$initiator_1_slave_resp_getResp,
                the_switch$target_0_master_resp_putResp_resp,
                the_switch$target_1_master_resp_putResp_resp;
  wire the_switch$initiator_0_slave_req_reqAccept,
       the_switch$initiator_0_slave_resp_respAccept_accept,
       the_switch$initiator_1_slave_req_reqAccept,
       the_switch$initiator_1_slave_resp_respAccept_accept,
       the_switch$target_0_master_req_reqAccept_accept,
       the_switch$target_0_master_resp_respAccept,
       the_switch$target_1_master_req_reqAccept_accept,
       the_switch$target_1_master_resp_respAccept;
  mkSwitch the_switch(.CLK(CLK),
                      .RST_N(RST_N),
                      .initiator_0_slave_req_putReq_req(the_switch$initiator_0_slave_req_putReq_req),
                      .initiator_0_slave_resp_respAccept_accept(the_switch$initiator_0_slave_resp_respAccept_accept),
                      .initiator_1_slave_req_putReq_req(the_switch$initiator_1_slave_req_putReq_req),
                      .initiator_1_slave_resp_respAccept_accept(the_switch$initiator_1_slave_resp_respAccept_accept),
                      .target_0_master_req_reqAccept_accept(the_switch$target_0_master_req_reqAccept_accept),
                      .target_0_master_resp_putResp_resp(the_switch$target_0_master_resp_putResp_resp),
                      .target_1_master_req_reqAccept_accept(the_switch$target_1_master_req_reqAccept_accept),
                      .target_1_master_resp_putResp_resp(the_switch$target_1_master_resp_putResp_resp),
                      .initiator_0_slave_req_reqAccept(the_switch$initiator_0_slave_req_reqAccept),
                      .initiator_0_slave_resp_getResp(the_switch$initiator_0_slave_resp_getResp),
                      .initiator_1_slave_req_reqAccept(the_switch$initiator_1_slave_req_reqAccept),
                      .initiator_1_slave_resp_getResp(the_switch$initiator_1_slave_resp_getResp),
                      .target_0_master_req_getReq(the_switch$target_0_master_req_getReq),
                      .target_0_master_resp_respAccept(the_switch$target_0_master_resp_respAccept),
                      .target_1_master_req_getReq(the_switch$target_1_master_req_getReq),
                      .target_1_master_resp_respAccept(the_switch$target_1_master_resp_respAccept));

  // rule scheduling signals
  wire CAN_FIRE_RL_initiator_0_accept_resps_from_0,
       CAN_FIRE_RL_initiator_0_accept_resps_from_1,
       CAN_FIRE_RL_initiator_0_gen_reqs,
       CAN_FIRE_RL_initiator_0_reqs_rule_update_final,
       CAN_FIRE_RL_initiator_0_resps_rule_update_final,
       CAN_FIRE_RL_initiator_1_accept_resps_from_0,
       CAN_FIRE_RL_initiator_1_accept_resps_from_1,
       CAN_FIRE_RL_initiator_1_gen_reqs,
       CAN_FIRE_RL_initiator_1_reqs_rule_update_final,
       CAN_FIRE_RL_initiator_1_resps_rule_update_final,
       CAN_FIRE_RL_relay_req,
       CAN_FIRE_RL_relay_req_1,
       CAN_FIRE_RL_relay_req_2,
       CAN_FIRE_RL_relay_req_3,
       CAN_FIRE_RL_relay_resp,
       CAN_FIRE_RL_relay_resp_1,
       CAN_FIRE_RL_relay_resp_2,
       CAN_FIRE_RL_relay_resp_3,
       CAN_FIRE_RL_target_0_reqs_rule_update_final,
       CAN_FIRE_RL_target_0_respond,
       CAN_FIRE_RL_target_0_resps_rule_update_final,
       CAN_FIRE_RL_target_1_reqs_rule_update_final,
       CAN_FIRE_RL_target_1_respond,
       CAN_FIRE_RL_target_1_resps_rule_update_final,
       WILL_FIRE_RL_initiator_0_accept_resps_from_0,
       WILL_FIRE_RL_initiator_0_accept_resps_from_1,
       WILL_FIRE_RL_initiator_0_gen_reqs,
       WILL_FIRE_RL_initiator_0_reqs_rule_update_final,
       WILL_FIRE_RL_initiator_0_resps_rule_update_final,
       WILL_FIRE_RL_initiator_1_accept_resps_from_0,
       WILL_FIRE_RL_initiator_1_accept_resps_from_1,
       WILL_FIRE_RL_initiator_1_gen_reqs,
       WILL_FIRE_RL_initiator_1_reqs_rule_update_final,
       WILL_FIRE_RL_initiator_1_resps_rule_update_final,
       WILL_FIRE_RL_relay_req,
       WILL_FIRE_RL_relay_req_1,
       WILL_FIRE_RL_relay_req_2,
       WILL_FIRE_RL_relay_req_3,
       WILL_FIRE_RL_relay_resp,
       WILL_FIRE_RL_relay_resp_1,
       WILL_FIRE_RL_relay_resp_2,
       WILL_FIRE_RL_relay_resp_3,
       WILL_FIRE_RL_target_0_reqs_rule_update_final,
       WILL_FIRE_RL_target_0_respond,
       WILL_FIRE_RL_target_0_resps_rule_update_final,
       WILL_FIRE_RL_target_1_reqs_rule_update_final,
       WILL_FIRE_RL_target_1_respond,
       WILL_FIRE_RL_target_1_resps_rule_update_final;

  // remaining internal signals
  wire [31 : 0] req_reqAddr__h1916,
                req_reqAddr__h536,
                req_reqData__h1917,
                req_reqData__h537;
  wire [1 : 0] IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351,
               IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352;
  wire NOT_IF_NOT_initiator_0_rand32_r_85_AND_7_86_UL_ETC___d297,
       NOT_IF_NOT_initiator_1_rand32_r_83_AND_7_84_UL_ETC___d195,
       NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275,
       NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250,
       NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173,
       NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148,
       initiator_0_expected_resps_0_first__60_BITS_31_ETC___d271,
       initiator_0_expected_resps_0_first__60_BITS_42_ETC___d265,
       initiator_0_expected_resps_0_first__60_BIT_32__ETC___d268,
       initiator_0_expected_resps_0_first__60_BIT_43__ETC___d262,
       initiator_0_expected_resps_1_first__35_BITS_31_ETC___d246,
       initiator_0_expected_resps_1_first__35_BITS_42_ETC___d240,
       initiator_0_expected_resps_1_first__35_BIT_32__ETC___d243,
       initiator_0_expected_resps_1_first__35_BIT_43__ETC___d237,
       initiator_1_expected_resps_0_first__58_BITS_31_ETC___d169,
       initiator_1_expected_resps_0_first__58_BITS_42_ETC___d163,
       initiator_1_expected_resps_0_first__58_BIT_32__ETC___d166,
       initiator_1_expected_resps_0_first__58_BIT_43__ETC___d160,
       initiator_1_expected_resps_1_first__33_BITS_31_ETC___d144,
       initiator_1_expected_resps_1_first__33_BITS_42_ETC___d138,
       initiator_1_expected_resps_1_first__33_BIT_32__ETC___d141,
       initiator_1_expected_resps_1_first__33_BIT_43__ETC___d135;

  // rule RL_relay_resp_3
  assign WILL_FIRE_RL_relay_resp_3 = 1'd1 ;
  assign CAN_FIRE_RL_relay_resp_3 = 1'd1 ;

  // rule RL_relay_resp_2
  assign WILL_FIRE_RL_relay_resp_2 = 1'd1 ;
  assign CAN_FIRE_RL_relay_resp_2 = 1'd1 ;

  // rule RL_relay_req_1
  assign WILL_FIRE_RL_relay_req_1 = 1'd1 ;
  assign CAN_FIRE_RL_relay_req_1 = 1'd1 ;

  // rule RL_relay_req
  assign WILL_FIRE_RL_relay_req = 1'd1 ;
  assign CAN_FIRE_RL_relay_req = 1'd1 ;

  // rule RL_target_1_respond
  assign WILL_FIRE_RL_target_1_respond =
             target_1_reqs_taggedReg[76] &&
             (target_1_reqs_taggedReg[75:74] != 2'd2 ||
              !target_1_resps_taggedReg[44] ||
              target_1_resps_pw_deq$whas) ;
  assign CAN_FIRE_RL_target_1_respond = WILL_FIRE_RL_target_1_respond ;

  // rule RL_relay_req_3
  assign WILL_FIRE_RL_relay_req_3 = 1'd1 ;
  assign CAN_FIRE_RL_relay_req_3 = 1'd1 ;

  // rule RL_target_1_resps_rule_update_final
  assign WILL_FIRE_RL_target_1_resps_rule_update_final =
             target_1_resps_rw_enq$whas || target_1_resps_pw_deq$whas ;
  assign CAN_FIRE_RL_target_1_resps_rule_update_final =
             WILL_FIRE_RL_target_1_resps_rule_update_final ;

  // rule RL_target_1_reqs_rule_update_final
  assign WILL_FIRE_RL_target_1_reqs_rule_update_final =
             target_1_reqs_rw_enq$whas || WILL_FIRE_RL_target_1_respond ;
  assign CAN_FIRE_RL_target_1_reqs_rule_update_final =
             WILL_FIRE_RL_target_1_reqs_rule_update_final ;

  // rule RL_target_0_respond
  assign WILL_FIRE_RL_target_0_respond =
             target_0_reqs_taggedReg[76] &&
             (target_0_reqs_taggedReg[75:74] != 2'd2 ||
              !target_0_resps_taggedReg[44] ||
              target_0_resps_pw_deq$whas) ;
  assign CAN_FIRE_RL_target_0_respond = WILL_FIRE_RL_target_0_respond ;

  // rule RL_relay_req_2
  assign WILL_FIRE_RL_relay_req_2 = 1'd1 ;
  assign CAN_FIRE_RL_relay_req_2 = 1'd1 ;

  // rule RL_target_0_resps_rule_update_final
  assign WILL_FIRE_RL_target_0_resps_rule_update_final =
             target_0_resps_rw_enq$whas || target_0_resps_pw_deq$whas ;
  assign CAN_FIRE_RL_target_0_resps_rule_update_final =
             WILL_FIRE_RL_target_0_resps_rule_update_final ;

  // rule RL_target_0_reqs_rule_update_final
  assign WILL_FIRE_RL_target_0_reqs_rule_update_final =
             target_0_reqs_rw_enq$whas || WILL_FIRE_RL_target_0_respond ;
  assign CAN_FIRE_RL_target_0_reqs_rule_update_final =
             WILL_FIRE_RL_target_0_reqs_rule_update_final ;

  // rule RL_initiator_1_accept_resps_from_1
  assign WILL_FIRE_RL_initiator_1_accept_resps_from_1 =
             initiator_1_resps_taggedReg[44] &&
             initiator_1_expected_resps_1$EMPTY_N &&
             initiator_1_resps_taggedReg[42:33] != 10'd0 ;
  assign CAN_FIRE_RL_initiator_1_accept_resps_from_1 =
             WILL_FIRE_RL_initiator_1_accept_resps_from_1 ;

  // rule RL_initiator_1_accept_resps_from_0
  assign WILL_FIRE_RL_initiator_1_accept_resps_from_0 =
             initiator_1_resps_taggedReg[44] &&
             initiator_1_expected_resps_0$EMPTY_N &&
             initiator_1_resps_taggedReg[42:33] == 10'd0 ;
  assign CAN_FIRE_RL_initiator_1_accept_resps_from_0 =
             WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;

  // rule RL_relay_resp_1
  assign WILL_FIRE_RL_relay_resp_1 = 1'd1 ;
  assign CAN_FIRE_RL_relay_resp_1 = 1'd1 ;

  // rule RL_initiator_1_gen_reqs
  assign WILL_FIRE_RL_initiator_1_gen_reqs =
             (!initiator_1_reqs_taggedReg[76] ||
              initiator_1_reqs_pw_deq$whas) &&
             NOT_IF_NOT_initiator_1_rand32_r_83_AND_7_84_UL_ETC___d195 ;
  assign CAN_FIRE_RL_initiator_1_gen_reqs =
             WILL_FIRE_RL_initiator_1_gen_reqs ;

  // rule RL_initiator_1_resps_rule_update_final
  assign WILL_FIRE_RL_initiator_1_resps_rule_update_final =
             initiator_1_resps_rw_enq$whas || initiator_1_resps_pw_deq$whas ;
  assign CAN_FIRE_RL_initiator_1_resps_rule_update_final =
             WILL_FIRE_RL_initiator_1_resps_rule_update_final ;

  // rule RL_initiator_1_reqs_rule_update_final
  assign WILL_FIRE_RL_initiator_1_reqs_rule_update_final =
             WILL_FIRE_RL_initiator_1_gen_reqs ||
             initiator_1_reqs_pw_deq$whas ;
  assign CAN_FIRE_RL_initiator_1_reqs_rule_update_final =
             WILL_FIRE_RL_initiator_1_reqs_rule_update_final ;

  // rule RL_initiator_0_accept_resps_from_1
  assign WILL_FIRE_RL_initiator_0_accept_resps_from_1 =
             initiator_0_resps_taggedReg[44] &&
             initiator_0_expected_resps_1$EMPTY_N &&
             initiator_0_resps_taggedReg[42:33] != 10'd0 ;
  assign CAN_FIRE_RL_initiator_0_accept_resps_from_1 =
             WILL_FIRE_RL_initiator_0_accept_resps_from_1 ;

  // rule RL_initiator_0_accept_resps_from_0
  assign WILL_FIRE_RL_initiator_0_accept_resps_from_0 =
             initiator_0_resps_taggedReg[44] &&
             initiator_0_expected_resps_0$EMPTY_N &&
             initiator_0_resps_taggedReg[42:33] == 10'd0 ;
  assign CAN_FIRE_RL_initiator_0_accept_resps_from_0 =
             WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;

  // rule RL_relay_resp
  assign WILL_FIRE_RL_relay_resp = 1'd1 ;
  assign CAN_FIRE_RL_relay_resp = 1'd1 ;

  // rule RL_initiator_0_gen_reqs
  assign WILL_FIRE_RL_initiator_0_gen_reqs =
             (!initiator_0_reqs_taggedReg[76] ||
              initiator_0_reqs_pw_deq$whas) &&
             NOT_IF_NOT_initiator_0_rand32_r_85_AND_7_86_UL_ETC___d297 ;
  assign CAN_FIRE_RL_initiator_0_gen_reqs =
             WILL_FIRE_RL_initiator_0_gen_reqs ;

  // rule RL_initiator_0_resps_rule_update_final
  assign WILL_FIRE_RL_initiator_0_resps_rule_update_final =
             initiator_0_resps_rw_enq$whas || initiator_0_resps_pw_deq$whas ;
  assign CAN_FIRE_RL_initiator_0_resps_rule_update_final =
             WILL_FIRE_RL_initiator_0_resps_rule_update_final ;

  // rule RL_initiator_0_reqs_rule_update_final
  assign WILL_FIRE_RL_initiator_0_reqs_rule_update_final =
             WILL_FIRE_RL_initiator_0_gen_reqs ||
             initiator_0_reqs_pw_deq$whas ;
  assign CAN_FIRE_RL_initiator_0_reqs_rule_update_final =
             WILL_FIRE_RL_initiator_0_reqs_rule_update_final ;

  // inlined wires
  assign initiator_0_reqs_rw_enq$wget =
             { IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351,
               10'd0,
               req_reqAddr__h536,
               req_reqData__h537 } ;
  assign initiator_0_reqs_pw_deq$whas =
             the_switch$initiator_0_slave_req_reqAccept &&
             initiator_0_reqs_taggedReg[76] ;
  assign initiator_0_resps_pw_deq$whas =
             WILL_FIRE_RL_initiator_0_accept_resps_from_1 ||
             WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;
  assign initiator_0_resps_rw_enq$whas =
             the_switch$initiator_0_slave_resp_getResp[43] &&
             (!initiator_0_resps_taggedReg[44] ||
              initiator_0_resps_pw_deq$whas) ;
  assign initiator_1_reqs_rw_enq$wget =
             { IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352,
               10'd1,
               req_reqAddr__h1916,
               req_reqData__h1917 } ;
  assign initiator_1_reqs_pw_deq$whas =
             the_switch$initiator_1_slave_req_reqAccept &&
             initiator_1_reqs_taggedReg[76] ;
  assign initiator_1_resps_pw_deq$whas =
             WILL_FIRE_RL_initiator_1_accept_resps_from_1 ||
             WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;
  assign initiator_1_resps_rw_enq$whas =
             the_switch$initiator_1_slave_resp_getResp[43] &&
             (!initiator_1_resps_taggedReg[44] ||
              initiator_1_resps_pw_deq$whas) ;
  assign target_0_resps_rw_enq$wget =
             { 11'd1024,
               target_0_reqs_taggedReg[64],
               target_0_reqs_taggedReg[31:0] } ;
  assign target_1_resps_pw_deq$whas =
             the_switch$target_1_master_resp_respAccept &&
             target_1_resps_taggedReg[44] ;
  assign target_0_resps_pw_deq$whas =
             the_switch$target_0_master_resp_respAccept &&
             target_0_resps_taggedReg[44] ;
  assign target_0_reqs_rw_enq$whas =
             the_switch$target_0_master_req_getReq[75:74] != 2'd0 &&
             (!target_0_reqs_taggedReg[76] || WILL_FIRE_RL_target_0_respond) ;
  assign target_0_resps_rw_enq$whas =
             WILL_FIRE_RL_target_0_respond &&
             target_0_reqs_taggedReg[75:74] == 2'd2 ;
  assign target_1_resps_rw_enq$whas =
             WILL_FIRE_RL_target_1_respond &&
             target_1_reqs_taggedReg[75:74] == 2'd2 ;
  assign target_1_reqs_rw_enq$whas =
             the_switch$target_1_master_req_getReq[75:74] != 2'd0 &&
             (!target_1_reqs_taggedReg[76] || WILL_FIRE_RL_target_1_respond) ;
  assign target_1_resps_rw_enq$wget =
             { 11'd1025,
               target_1_reqs_taggedReg[64],
               target_1_reqs_taggedReg[31:0] } ;

  // register initiator_0_rand32_r
  assign initiator_0_rand32_r$D_IN =
             initiator_0_rand32_r[0] ?
               { 1'd0, initiator_0_rand32_r[31:1] } ^ 32'h80000057 :
               { 1'd0, initiator_0_rand32_r[31:1] } ;
  assign initiator_0_rand32_r$EN = WILL_FIRE_RL_initiator_0_gen_reqs ;

  // register initiator_0_reqs_taggedReg
  assign initiator_0_reqs_taggedReg$D_IN =
             { WILL_FIRE_RL_initiator_0_gen_reqs,
               initiator_0_reqs_rw_enq$wget } ;
  assign initiator_0_reqs_taggedReg$EN =
             WILL_FIRE_RL_initiator_0_reqs_rule_update_final ;

  // register initiator_0_resps_taggedReg
  assign initiator_0_resps_taggedReg$D_IN =
             { initiator_0_resps_rw_enq$whas,
               the_switch$initiator_0_slave_resp_getResp } ;
  assign initiator_0_resps_taggedReg$EN =
             WILL_FIRE_RL_initiator_0_resps_rule_update_final ;

  // register initiator_1_rand32_r
  assign initiator_1_rand32_r$D_IN =
             initiator_1_rand32_r[0] ?
               { 1'd0, initiator_1_rand32_r[31:1] } ^ 32'h80000062 :
               { 1'd0, initiator_1_rand32_r[31:1] } ;
  assign initiator_1_rand32_r$EN = WILL_FIRE_RL_initiator_1_gen_reqs ;

  // register initiator_1_reqs_taggedReg
  assign initiator_1_reqs_taggedReg$D_IN =
             { WILL_FIRE_RL_initiator_1_gen_reqs,
               initiator_1_reqs_rw_enq$wget } ;
  assign initiator_1_reqs_taggedReg$EN =
             WILL_FIRE_RL_initiator_1_reqs_rule_update_final ;

  // register initiator_1_resps_taggedReg
  assign initiator_1_resps_taggedReg$D_IN =
             { initiator_1_resps_rw_enq$whas,
               the_switch$initiator_1_slave_resp_getResp } ;
  assign initiator_1_resps_taggedReg$EN =
             WILL_FIRE_RL_initiator_1_resps_rule_update_final ;

  // register target_0_reqs_taggedReg
  assign target_0_reqs_taggedReg$D_IN =
             { target_0_reqs_rw_enq$whas,
               the_switch$target_0_master_req_getReq } ;
  assign target_0_reqs_taggedReg$EN =
             WILL_FIRE_RL_target_0_reqs_rule_update_final ;

  // register target_0_resps_taggedReg
  assign target_0_resps_taggedReg$D_IN =
             { target_0_resps_rw_enq$whas, target_0_resps_rw_enq$wget } ;
  assign target_0_resps_taggedReg$EN =
             WILL_FIRE_RL_target_0_resps_rule_update_final ;

  // register target_1_reqs_taggedReg
  assign target_1_reqs_taggedReg$D_IN =
             { target_1_reqs_rw_enq$whas,
               the_switch$target_1_master_req_getReq } ;
  assign target_1_reqs_taggedReg$EN =
             WILL_FIRE_RL_target_1_reqs_rule_update_final ;

  // register target_1_resps_taggedReg
  assign target_1_resps_taggedReg$EN =
             WILL_FIRE_RL_target_1_resps_rule_update_final ;
  assign target_1_resps_taggedReg$D_IN =
             { target_1_resps_rw_enq$whas, target_1_resps_rw_enq$wget } ;

  // submodule initiator_0_expected_resps_0
  assign initiator_0_expected_resps_0$D_IN =
             { 28'd134217728, initiator_0_rand32_r[31:16] } ;
  assign initiator_0_expected_resps_0$DEQ =
             WILL_FIRE_RL_initiator_0_accept_resps_from_0 ;
  assign initiator_0_expected_resps_0$ENQ =
             WILL_FIRE_RL_initiator_0_gen_reqs &&
             IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 ==
             2'd2 &&
             !initiator_0_rand32_r[4] ;
  assign initiator_0_expected_resps_0$CLR = 1'b0 ;

  // submodule initiator_0_expected_resps_1
  assign initiator_0_expected_resps_1$D_IN =
             { 28'd134348800, initiator_0_rand32_r[31:16] } ;
  assign initiator_0_expected_resps_1$DEQ =
             WILL_FIRE_RL_initiator_0_accept_resps_from_1 ;
  assign initiator_0_expected_resps_1$ENQ =
             WILL_FIRE_RL_initiator_0_gen_reqs &&
             IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 ==
             2'd2 &&
             initiator_0_rand32_r[4] ;
  assign initiator_0_expected_resps_1$CLR = 1'b0 ;

  // submodule initiator_1_expected_resps_0
  assign initiator_1_expected_resps_0$D_IN =
             { 28'd134283264, initiator_1_rand32_r[31:16] } ;
  assign initiator_1_expected_resps_0$DEQ =
             WILL_FIRE_RL_initiator_1_accept_resps_from_0 ;
  assign initiator_1_expected_resps_0$ENQ =
             WILL_FIRE_RL_initiator_1_gen_reqs &&
             IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 ==
             2'd2 &&
             !initiator_1_rand32_r[4] ;
  assign initiator_1_expected_resps_0$CLR = 1'b0 ;

  // submodule initiator_1_expected_resps_1
  assign initiator_1_expected_resps_1$D_IN =
             { 28'd134414336, initiator_1_rand32_r[31:16] } ;
  assign initiator_1_expected_resps_1$DEQ =
             WILL_FIRE_RL_initiator_1_accept_resps_from_1 ;
  assign initiator_1_expected_resps_1$ENQ =
             WILL_FIRE_RL_initiator_1_gen_reqs &&
             IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 ==
             2'd2 &&
             initiator_1_rand32_r[4] ;
  assign initiator_1_expected_resps_1$CLR = 1'b0 ;

  // submodule the_switch
  assign the_switch$initiator_0_slave_req_putReq_req =
             { initiator_0_reqs_taggedReg[76] ?
                 initiator_0_reqs_taggedReg[75:74] :
                 2'd0,
               initiator_0_reqs_taggedReg[73:0] } ;
  assign the_switch$initiator_1_slave_req_putReq_req =
             { initiator_1_reqs_taggedReg[76] ?
                 initiator_1_reqs_taggedReg[75:74] :
                 2'd0,
               initiator_1_reqs_taggedReg[73:0] } ;
  assign the_switch$target_0_master_resp_putResp_resp =
             { target_0_resps_taggedReg[44] && target_0_resps_taggedReg[43],
               target_0_resps_taggedReg[42:0] } ;
  assign the_switch$target_1_master_resp_putResp_resp =
             { target_1_resps_taggedReg[44] && target_1_resps_taggedReg[43],
               target_1_resps_taggedReg[42:0] } ;
  assign the_switch$initiator_0_slave_resp_respAccept_accept =
             !initiator_0_resps_taggedReg[44] ||
             initiator_0_resps_pw_deq$whas ;
  assign the_switch$initiator_1_slave_resp_respAccept_accept =
             !initiator_1_resps_taggedReg[44] ||
             initiator_1_resps_pw_deq$whas ;
  assign the_switch$target_1_master_req_reqAccept_accept =
             !target_1_reqs_taggedReg[76] || WILL_FIRE_RL_target_1_respond ;
  assign the_switch$target_0_master_req_reqAccept_accept =
             !target_0_reqs_taggedReg[76] || WILL_FIRE_RL_target_0_respond ;

  // remaining internal signals
  assign IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 =
             ((initiator_0_rand32_r & 32'd7) <= 32'd5) ? 2'd2 : 2'd1 ;
  assign IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 =
             ((initiator_1_rand32_r & 32'd7) <= 32'd5) ? 2'd2 : 2'd1 ;
  assign NOT_IF_NOT_initiator_0_rand32_r_85_AND_7_86_UL_ETC___d297 =
             IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 !=
             2'd2 ||
             (initiator_0_rand32_r[4] ?
                initiator_0_expected_resps_1$FULL_N :
                initiator_0_expected_resps_0$FULL_N) ;
  assign NOT_IF_NOT_initiator_1_rand32_r_83_AND_7_84_UL_ETC___d195 =
             IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 !=
             2'd2 ||
             (initiator_1_rand32_r[4] ?
                initiator_1_expected_resps_1$FULL_N :
                initiator_1_expected_resps_0$FULL_N) ;
  assign NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275 =
             !initiator_0_expected_resps_0_first__60_BIT_43__ETC___d262 ||
             !initiator_0_expected_resps_0_first__60_BITS_42_ETC___d265 ||
             !initiator_0_expected_resps_0_first__60_BIT_32__ETC___d268 ||
             !initiator_0_expected_resps_0_first__60_BITS_31_ETC___d271 ;
  assign NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250 =
             !initiator_0_expected_resps_1_first__35_BIT_43__ETC___d237 ||
             !initiator_0_expected_resps_1_first__35_BITS_42_ETC___d240 ||
             !initiator_0_expected_resps_1_first__35_BIT_32__ETC___d243 ||
             !initiator_0_expected_resps_1_first__35_BITS_31_ETC___d246 ;
  assign NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173 =
             !initiator_1_expected_resps_0_first__58_BIT_43__ETC___d160 ||
             !initiator_1_expected_resps_0_first__58_BITS_42_ETC___d163 ||
             !initiator_1_expected_resps_0_first__58_BIT_32__ETC___d166 ||
             !initiator_1_expected_resps_0_first__58_BITS_31_ETC___d169 ;
  assign NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148 =
             !initiator_1_expected_resps_1_first__33_BIT_43__ETC___d135 ||
             !initiator_1_expected_resps_1_first__33_BITS_42_ETC___d138 ||
             !initiator_1_expected_resps_1_first__33_BIT_32__ETC___d141 ||
             !initiator_1_expected_resps_1_first__33_BITS_31_ETC___d144 ;
  assign initiator_0_expected_resps_0_first__60_BITS_31_ETC___d271 =
             initiator_0_expected_resps_0$D_OUT[31:0] ==
             initiator_0_resps_taggedReg[31:0] ;
  assign initiator_0_expected_resps_0_first__60_BITS_42_ETC___d265 =
             initiator_0_expected_resps_0$D_OUT[42:33] ==
             initiator_0_resps_taggedReg[42:33] ;
  assign initiator_0_expected_resps_0_first__60_BIT_32__ETC___d268 =
             initiator_0_expected_resps_0$D_OUT[32] ==
             initiator_0_resps_taggedReg[32] ;
  assign initiator_0_expected_resps_0_first__60_BIT_43__ETC___d262 =
             initiator_0_expected_resps_0$D_OUT[43] ==
             initiator_0_resps_taggedReg[43] ;
  assign initiator_0_expected_resps_1_first__35_BITS_31_ETC___d246 =
             initiator_0_expected_resps_1$D_OUT[31:0] ==
             initiator_0_resps_taggedReg[31:0] ;
  assign initiator_0_expected_resps_1_first__35_BITS_42_ETC___d240 =
             initiator_0_expected_resps_1$D_OUT[42:33] ==
             initiator_0_resps_taggedReg[42:33] ;
  assign initiator_0_expected_resps_1_first__35_BIT_32__ETC___d243 =
             initiator_0_expected_resps_1$D_OUT[32] ==
             initiator_0_resps_taggedReg[32] ;
  assign initiator_0_expected_resps_1_first__35_BIT_43__ETC___d237 =
             initiator_0_expected_resps_1$D_OUT[43] ==
             initiator_0_resps_taggedReg[43] ;
  assign initiator_1_expected_resps_0_first__58_BITS_31_ETC___d169 =
             initiator_1_expected_resps_0$D_OUT[31:0] ==
             initiator_1_resps_taggedReg[31:0] ;
  assign initiator_1_expected_resps_0_first__58_BITS_42_ETC___d163 =
             initiator_1_expected_resps_0$D_OUT[42:33] ==
             initiator_1_resps_taggedReg[42:33] ;
  assign initiator_1_expected_resps_0_first__58_BIT_32__ETC___d166 =
             initiator_1_expected_resps_0$D_OUT[32] ==
             initiator_1_resps_taggedReg[32] ;
  assign initiator_1_expected_resps_0_first__58_BIT_43__ETC___d160 =
             initiator_1_expected_resps_0$D_OUT[43] ==
             initiator_1_resps_taggedReg[43] ;
  assign initiator_1_expected_resps_1_first__33_BITS_31_ETC___d144 =
             initiator_1_expected_resps_1$D_OUT[31:0] ==
             initiator_1_resps_taggedReg[31:0] ;
  assign initiator_1_expected_resps_1_first__33_BITS_42_ETC___d138 =
             initiator_1_expected_resps_1$D_OUT[42:33] ==
             initiator_1_resps_taggedReg[42:33] ;
  assign initiator_1_expected_resps_1_first__33_BIT_32__ETC___d141 =
             initiator_1_expected_resps_1$D_OUT[32] ==
             initiator_1_resps_taggedReg[32] ;
  assign initiator_1_expected_resps_1_first__33_BIT_43__ETC___d135 =
             initiator_1_expected_resps_1$D_OUT[43] ==
             initiator_1_resps_taggedReg[43] ;
  assign req_reqAddr__h1916 = { 20'd0, initiator_1_rand32_r[15:4] } ;
  assign req_reqAddr__h536 = { 20'd0, initiator_0_rand32_r[15:4] } ;
  assign req_reqData__h1917 = { 16'd0, initiator_1_rand32_r[31:16] } ;
  assign req_reqData__h537 = { 16'd0, initiator_0_rand32_r[31:16] } ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        initiator_0_rand32_r <= `BSV_ASSIGNMENT_DELAY 32'd1;
        initiator_0_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        initiator_0_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        initiator_1_rand32_r <= `BSV_ASSIGNMENT_DELAY 32'd1;
        initiator_1_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        initiator_1_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        target_0_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        target_0_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        target_1_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        target_1_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
      end
    else
      begin
        if (initiator_0_rand32_r$EN)
          initiator_0_rand32_r <= `BSV_ASSIGNMENT_DELAY
              initiator_0_rand32_r$D_IN;
        if (initiator_0_reqs_taggedReg$EN)
          initiator_0_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
              initiator_0_reqs_taggedReg$D_IN;
        if (initiator_0_resps_taggedReg$EN)
          initiator_0_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY
              initiator_0_resps_taggedReg$D_IN;
        if (initiator_1_rand32_r$EN)
          initiator_1_rand32_r <= `BSV_ASSIGNMENT_DELAY
              initiator_1_rand32_r$D_IN;
        if (initiator_1_reqs_taggedReg$EN)
          initiator_1_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
              initiator_1_reqs_taggedReg$D_IN;
        if (initiator_1_resps_taggedReg$EN)
          initiator_1_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY
              initiator_1_resps_taggedReg$D_IN;
        if (target_0_reqs_taggedReg$EN)
          target_0_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
              target_0_reqs_taggedReg$D_IN;
        if (target_0_resps_taggedReg$EN)
          target_0_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY
              target_0_resps_taggedReg$D_IN;
        if (target_1_reqs_taggedReg$EN)
          target_1_reqs_taggedReg <= `BSV_ASSIGNMENT_DELAY
              target_1_reqs_taggedReg$D_IN;
        if (target_1_resps_taggedReg$EN)
          target_1_resps_taggedReg <= `BSV_ASSIGNMENT_DELAY
              target_1_resps_taggedReg$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    initiator_0_rand32_r = 32'hAAAAAAAA;
    initiator_0_reqs_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    initiator_0_resps_taggedReg = 45'h0AAAAAAAAAAA;
    initiator_1_rand32_r = 32'hAAAAAAAA;
    initiator_1_reqs_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    initiator_1_resps_taggedReg = 45'h0AAAAAAAAAAA;
    target_0_reqs_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    target_0_resps_taggedReg = 45'h0AAAAAAAAAAA;
    target_1_reqs_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    target_1_resps_taggedReg = 45'h0AAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks
  
  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond)
        $write("Tb: target %d received request ", $signed(32'd1));
    if (RST_N) if (WILL_FIRE_RL_target_1_respond) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd0)
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd1)
        $write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] != 2'd0 &&
          target_1_reqs_taggedReg[75:74] != 2'd1)
        $write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] != 2'd0)
        $write(", %h, %h, %h}",
               target_1_reqs_taggedReg[73:64],
               target_1_reqs_taggedReg[63:32],
               target_1_reqs_taggedReg[31:0]);
    if (RST_N) if (WILL_FIRE_RL_target_1_respond) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd2)
        $write("              Sent response ");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd2)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd2)
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd2)
        $write(", %h, %h, %h",
               10'd1,
               target_1_reqs_taggedReg[64],
               target_1_reqs_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_target_1_respond &&
          target_1_reqs_taggedReg[75:74] == 2'd2)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond)
        $write("Tb: target %d received request ", $signed(32'd0));
    if (RST_N) if (WILL_FIRE_RL_target_0_respond) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd0)
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd1)
        $write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] != 2'd0 &&
          target_0_reqs_taggedReg[75:74] != 2'd1)
        $write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] != 2'd0)
        $write(", %h, %h, %h}",
               target_0_reqs_taggedReg[73:64],
               target_0_reqs_taggedReg[63:32],
               target_0_reqs_taggedReg[31:0]);
    if (RST_N) if (WILL_FIRE_RL_target_0_respond) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd2)
        $write("              Sent response ");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd2)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd2)
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd2)
        $write(", %h, %h, %h",
               10'd0,
               target_0_reqs_taggedReg[64],
               target_0_reqs_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_target_0_respond &&
          target_0_reqs_taggedReg[75:74] == 2'd2)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1)
        $write("Tb: initiator %d received response ", $signed(32'd1));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          !initiator_1_resps_taggedReg[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          initiator_1_resps_taggedReg[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          initiator_1_resps_taggedReg[43])
        $write(", %h, %h, %h",
               initiator_1_resps_taggedReg[42:33],
               initiator_1_resps_taggedReg[32],
               initiator_1_resps_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148)
        $write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148 &&
          !initiator_1_expected_resps_1$D_OUT[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148 &&
          initiator_1_expected_resps_1$D_OUT[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148 &&
          initiator_1_expected_resps_1$D_OUT[43])
        $write(", %h, %h, %h",
               initiator_1_expected_resps_1$D_OUT[42:33],
               initiator_1_expected_resps_1$D_OUT[32],
               initiator_1_expected_resps_1$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          NOT_initiator_1_expected_resps_1_first__33_BIT_ETC___d148)
        $finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_1 &&
          initiator_1_expected_resps_1_first__33_BIT_43__ETC___d135 &&
          initiator_1_expected_resps_1_first__33_BITS_42_ETC___d138 &&
          initiator_1_expected_resps_1_first__33_BIT_32__ETC___d141 &&
          initiator_1_expected_resps_1_first__33_BITS_31_ETC___d144)
        $display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0)
        $write("Tb: initiator %d received response ", $signed(32'd1));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          !initiator_1_resps_taggedReg[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          initiator_1_resps_taggedReg[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          initiator_1_resps_taggedReg[43])
        $write(", %h, %h, %h",
               initiator_1_resps_taggedReg[42:33],
               initiator_1_resps_taggedReg[32],
               initiator_1_resps_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173)
        $write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173 &&
          !initiator_1_expected_resps_0$D_OUT[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173 &&
          initiator_1_expected_resps_0$D_OUT[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173 &&
          initiator_1_expected_resps_0$D_OUT[43])
        $write(", %h, %h, %h",
               initiator_1_expected_resps_0$D_OUT[42:33],
               initiator_1_expected_resps_0$D_OUT[32],
               initiator_1_expected_resps_0$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          NOT_initiator_1_expected_resps_0_first__58_BIT_ETC___d173)
        $finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_accept_resps_from_0 &&
          initiator_1_expected_resps_0_first__58_BIT_43__ETC___d160 &&
          initiator_1_expected_resps_0_first__58_BITS_42_ETC___d163 &&
          initiator_1_expected_resps_0_first__58_BIT_32__ETC___d166 &&
          initiator_1_expected_resps_0_first__58_BITS_31_ETC___d169)
        $display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs)
        $write("Tb: initiator %d sent request ", $signed(32'd1));
    if (RST_N) if (WILL_FIRE_RL_initiator_1_gen_reqs) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
          IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 == 2'd0)
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
          IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 == 2'd1)
        $write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
          IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 != 2'd0 &&
          IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 != 2'd1)
        $write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_1_gen_reqs &&
          IF_NOT_initiator_1_rand32_r_83_AND_7_84_ULE_5__ETC___d352 != 2'd0)
        $write(", %h, %h, %h}",
               10'd1,
               req_reqAddr__h1916,
               req_reqData__h1917);
    if (RST_N) if (WILL_FIRE_RL_initiator_1_gen_reqs) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1)
        $write("Tb: initiator %d received response ", $signed(32'd0));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          !initiator_0_resps_taggedReg[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          initiator_0_resps_taggedReg[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          initiator_0_resps_taggedReg[43])
        $write(", %h, %h, %h",
               initiator_0_resps_taggedReg[42:33],
               initiator_0_resps_taggedReg[32],
               initiator_0_resps_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250)
        $write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250 &&
          !initiator_0_expected_resps_1$D_OUT[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250 &&
          initiator_0_expected_resps_1$D_OUT[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250 &&
          initiator_0_expected_resps_1$D_OUT[43])
        $write(", %h, %h, %h",
               initiator_0_expected_resps_1$D_OUT[42:33],
               initiator_0_expected_resps_1$D_OUT[32],
               initiator_0_expected_resps_1$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          NOT_initiator_0_expected_resps_1_first__35_BIT_ETC___d250)
        $finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_1 &&
          initiator_0_expected_resps_1_first__35_BIT_43__ETC___d237 &&
          initiator_0_expected_resps_1_first__35_BITS_42_ETC___d240 &&
          initiator_0_expected_resps_1_first__35_BIT_32__ETC___d243 &&
          initiator_0_expected_resps_1_first__35_BITS_31_ETC___d246)
        $display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0)
        $write("Tb: initiator %d received response ", $signed(32'd0));
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          !initiator_0_resps_taggedReg[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          initiator_0_resps_taggedReg[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          initiator_0_resps_taggedReg[43])
        $write(", %h, %h, %h",
               initiator_0_resps_taggedReg[42:33],
               initiator_0_resps_taggedReg[32],
               initiator_0_resps_taggedReg[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0) $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275)
        $write("ERROR: does not match expected response ");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275)
        $write("Socket_Resp{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275 &&
          !initiator_0_expected_resps_0$D_OUT[43])
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275 &&
          initiator_0_expected_resps_0$D_OUT[43])
        $write("OK");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275 &&
          initiator_0_expected_resps_0$D_OUT[43])
        $write(", %h, %h, %h",
               initiator_0_expected_resps_0$D_OUT[42:33],
               initiator_0_expected_resps_0$D_OUT[32],
               initiator_0_expected_resps_0$D_OUT[31:0]);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275)
        $display("}");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          NOT_initiator_0_expected_resps_0_first__60_BIT_ETC___d275)
        $finish(32'd1);
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_accept_resps_from_0 &&
          initiator_0_expected_resps_0_first__60_BIT_43__ETC___d262 &&
          initiator_0_expected_resps_0_first__60_BITS_42_ETC___d265 &&
          initiator_0_expected_resps_0_first__60_BIT_32__ETC___d268 &&
          initiator_0_expected_resps_0_first__60_BITS_31_ETC___d271)
        $display("    Response is ok");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs)
        $write("Tb: initiator %d sent request ", $signed(32'd0));
    if (RST_N) if (WILL_FIRE_RL_initiator_0_gen_reqs) $write("Socket_Req{");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
          IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 == 2'd0)
        $write("NOP");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
          IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 == 2'd1)
        $write("WR");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
          IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 != 2'd0 &&
          IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 != 2'd1)
        $write("RD");
    if (RST_N)
      if (WILL_FIRE_RL_initiator_0_gen_reqs &&
          IF_NOT_initiator_0_rand32_r_85_AND_7_86_ULE_5__ETC___d351 != 2'd0)
        $write(", %h, %h, %h}", 10'd0, req_reqAddr__h536, req_reqData__h537);
    if (RST_N) if (WILL_FIRE_RL_initiator_0_gen_reqs) $display("}");
  end
  // synopsys translate_on
endmodule  // mkTb

        