Synthesis Results Summary
-------------------------

Synthesis at 0.18um
-------------------

    Inputs/Assumptions
    ------------------

        Design Compiler Version: X-2005.09-SP3

        Technology: TSMC CL018G process
           Library: Artisan SAGE-X (SS Process Spice Models, 1.62V, 125 Degrees C)
    
        Added Input/Ouput delay = 25% of clock period.

    Results
    -------

        2X2 Switch
        ----------

        Frequency: 380 MHz
             Area:  6.50 Kgates, 64.87 Kum^2  (1 gate = 9.98 um^2)

        DMA
        ---

        Frequency: 286 MHz
             Area: 21.33 Kgates, 212.87 Kum^2  (1 gate = 9.98 um^2)

Synthesis at 65nm
-----------------

    Inputs/Assumptions
    ------------------

        Design Compiler Version: X-2005.09-SP3

        Technology: TSMC CLN65GP process
           Library: Artisan 10-Track Advantage (SS Process Spice Models, 0.90V, 125 Degrees C)
    
        Added Input/Ouput delay = 25% of clock period.

    Results
    -------

        2X2 Switch
        ----------

        Frequency: 1.11 GHz
             Area:  9.81 Kgates,  15.70 Kum^2  (1 gate = 1.60 um^2)

        DMA
        ---

        Frequency: 769 MHz
             Area: 27.77 Kgates,  44.43 Kum^2  (1 gate = 1.60 um^2)


