//
// Generated by Bluespec Compiler, version 2006.11 (build 9956, 2006-11-11)
// 
// On Mon Feb 12 11:58:18 EST 2007
// 
// Method conflict info:
// Method: enq
// Sequenced after: first
// Sequenced after (restricted): clear
// Conflicts: enq, deq
//  
// Method: deq
// Conflict-free: clear
// Sequenced after: first
// Conflicts: enq, deq
//  
// Method: first
// Conflict-free: first
// Sequenced before: enq, deq, clear
//  
// Method: clear
// Conflict-free: deq
// Sequenced before (restricted): enq
// Sequenced after: first
// Conflicts: clear
//  
// 
// Ports:
// Name                         I/O  size props
// RDY_enq                        O     1
// RDY_deq                        O     1
// first                          O    32
// RDY_first                      O     1
// RDY_clear                      O     1 const
// CLK                            I     1
// RST_N                          I     1
// enq_x1                         I    32
// EN_enq                         I     1
// EN_deq                         I     1
// EN_clear                       I     1
// 
// Combinational paths from inputs to outputs:
//   (EN_deq, EN_clear) -> RDY_enq
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkFifo4(CLK,
               RST_N,
               
               enq_x1,
               EN_enq,
               RDY_enq,
               
               EN_deq,
               RDY_deq,
               
               first,
               RDY_first,
               
               EN_clear,
               RDY_clear);
  input  CLK;
  input  RST_N;
  
  // action method enq
  input  [31 : 0] enq_x1;
  input  EN_enq;
  output RDY_enq;
  
  // action method deq
  input  EN_deq;
  output RDY_deq;
  
  // value method first
  output [31 : 0] first;
  output RDY_first;
  
  // action method clear
  input  EN_clear;
  output RDY_clear;

  // signals for module outputs
  reg [31 : 0] first;
  wire RDY_clear, RDY_deq, RDY_enq, RDY_first;

  // register f_rdPtr
  reg [1 : 0] f_rdPtr;
  wire [1 : 0] f_rdPtr$D_IN;
  wire f_rdPtr$EN;

  // register f_state
  reg [31 : 0] f_state;
  wire [31 : 0] f_state$D_IN;
  wire f_state$EN;

  // register f_state_1
  reg [31 : 0] f_state_1;
  wire [31 : 0] f_state_1$D_IN;
  wire f_state_1$EN;

  // register f_state_2
  reg [31 : 0] f_state_2;
  wire [31 : 0] f_state_2$D_IN;
  wire f_state_2$EN;

  // register f_state_3
  reg [31 : 0] f_state_3;
  wire [31 : 0] f_state_3$D_IN;
  wire f_state_3$EN;

  // register f_wrPtr
  reg [1 : 0] f_wrPtr;
  wire [1 : 0] f_wrPtr$D_IN;
  wire f_wrPtr$EN;

  // rule scheduling signals
  wire CAN_FIRE_clear,
       CAN_FIRE_deq,
       CAN_FIRE_enq,
       WILL_FIRE_clear,
       WILL_FIRE_deq,
       WILL_FIRE_enq;

  // inputs to muxes for submodule ports
  wire MUX_f_state$write_1__SEL_1,
       MUX_f_state_1$write_1__SEL_1,
       MUX_f_state_2$write_1__SEL_1,
       MUX_f_state_3$write_1__SEL_1;

  // action method enq
  assign RDY_enq = !EN_clear && (f_wrPtr - f_rdPtr != 2'd3 || EN_deq) ;
  assign CAN_FIRE_enq = RDY_enq ;
  assign WILL_FIRE_enq = EN_enq ;

  // action method deq
  assign RDY_deq = f_rdPtr != f_wrPtr ;
  assign CAN_FIRE_deq = f_rdPtr != f_wrPtr ;
  assign WILL_FIRE_deq = EN_deq ;

  // value method first
  always@(f_rdPtr or f_state_3 or f_state or f_state_1 or f_state_2)
  begin
    case (f_rdPtr)
      2'd0: first = f_state;
      2'd1: first = f_state_1;
      2'd2: first = f_state_2;
      2'd3: first = f_state_3;
    endcase
  end
  assign RDY_first = f_rdPtr != f_wrPtr ;

  // action method clear
  assign RDY_clear = 1'd1 ;
  assign CAN_FIRE_clear = 1'd1 ;
  assign WILL_FIRE_clear = EN_clear ;

  // inputs to muxes for submodule ports
  assign MUX_f_state$write_1__SEL_1 = EN_enq && f_wrPtr == 2'd0 ;
  assign MUX_f_state_1$write_1__SEL_1 = EN_enq && f_wrPtr == 2'd1 ;
  assign MUX_f_state_2$write_1__SEL_1 = EN_enq && f_wrPtr == 2'd2 ;
  assign MUX_f_state_3$write_1__SEL_1 =
             EN_enq && f_wrPtr != 2'd0 && f_wrPtr != 2'd1 && f_wrPtr != 2'd2 ;

  // register f_rdPtr
  assign f_rdPtr$D_IN = (f_rdPtr == 2'd3) ? 2'd0 : f_rdPtr + 2'd1 ;
  assign f_rdPtr$EN = EN_deq ;

  // register f_state
  assign f_state$D_IN = MUX_f_state$write_1__SEL_1 ? enq_x1 : 32'd0 ;
  assign f_state$EN = EN_enq && f_wrPtr == 2'd0 || EN_clear ;

  // register f_state_1
  assign f_state_1$D_IN = MUX_f_state_1$write_1__SEL_1 ? enq_x1 : 32'd0 ;
  assign f_state_1$EN = EN_enq && f_wrPtr == 2'd1 || EN_clear ;

  // register f_state_2
  assign f_state_2$D_IN = MUX_f_state_2$write_1__SEL_1 ? enq_x1 : 32'd0 ;
  assign f_state_2$EN = EN_enq && f_wrPtr == 2'd2 || EN_clear ;

  // register f_state_3
  assign f_state_3$D_IN = MUX_f_state_3$write_1__SEL_1 ? enq_x1 : 32'd0 ;
  assign f_state_3$EN =
             EN_enq && f_wrPtr != 2'd0 && f_wrPtr != 2'd1 &&
             f_wrPtr != 2'd2 ||
             EN_clear ;

  // register f_wrPtr
  assign f_wrPtr$D_IN = (f_wrPtr == 2'd3) ? 2'd0 : f_wrPtr + 2'd1 ;
  assign f_wrPtr$EN = EN_enq ;

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        f_rdPtr <= `BSV_ASSIGNMENT_DELAY 2'd0;
        f_state <= `BSV_ASSIGNMENT_DELAY 32'd0;
        f_state_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        f_state_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        f_state_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        f_wrPtr <= `BSV_ASSIGNMENT_DELAY 2'd0;
      end
    else
      begin
        if (f_rdPtr$EN) f_rdPtr <= `BSV_ASSIGNMENT_DELAY f_rdPtr$D_IN;
        if (f_state$EN) f_state <= `BSV_ASSIGNMENT_DELAY f_state$D_IN;
        if (f_state_1$EN) f_state_1 <= `BSV_ASSIGNMENT_DELAY f_state_1$D_IN;
        if (f_state_2$EN) f_state_2 <= `BSV_ASSIGNMENT_DELAY f_state_2$D_IN;
        if (f_state_3$EN) f_state_3 <= `BSV_ASSIGNMENT_DELAY f_state_3$D_IN;
        if (f_wrPtr$EN) f_wrPtr <= `BSV_ASSIGNMENT_DELAY f_wrPtr$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    f_rdPtr = 2'h2;
    f_state = 32'hAAAAAAAA;
    f_state_1 = 32'hAAAAAAAA;
    f_state_2 = 32'hAAAAAAAA;
    f_state_3 = 32'hAAAAAAAA;
    f_wrPtr = 2'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkFifo4

        