These are Bluespec's solutions for the Deepchip design challenge.

As a start, please review the two PDF documents in this directory --
one for each design:

Basic2x2Interconnect.pdf - this document outlines the specification
   for the 2x2 switch interconnect, provides an overview of Bluespec
   design, and summarizes the design of the switch.

Simple4ChannelDMAController.pdf - this document outlines the
   specification for the DMA controller, provides an overview of Bluespec
   design, and summarizes the design of the DMA.

In addition, there's a file summarizing the DC synthesis results for both
   designs, DCResultsSummary.txt.


There are also two directories:

Basic2x2Interconnect - this directory holds the design sources,
   generated Verilog files, and testbench log results for the 2x2 switch
   interconnect design.

DMA - this directory holds the design sources, generated Verilog
   files, and testbench log results for the DMA controller design.



Here is a summary of the rest of the files.

Under the directory Basic2x2Interconnect, there are five directories:


InitialVersion.v1: 
    There are three directories in this directory: 

    Sources:
       Makefile - makefile for compiling the files
       Socket_IFC.bsv - this file holds the definitions of the
          interfaces, types and functions for the socket interface
       Switch.bsv - this file is the source code for the switch design.
          This is the first version of the design.  It is a model of the
          design put together quickly
       Tb.bsv - this is the basic testbench
          for the switch

    TestLog:
       LOG - logfile from the test run

    Verilog:
       mkTb.v - the generated Verilog corresponding to Tb.bsv
       mkSwitch.v - the generated Verilog corresponding to Switch.bsv

v2:
    There are three directories in this directory: 

    Sources:
       Makefile - makefile for compiling the files
       Socket_IFC.bsv - this
          file holds the definitions of the interfaces, types and functions
          for the socket interface
       Switch.bsv - this file is the source code
          for the switch design.  This is the second version of the design.
          It represents the first refinement step
       Tb.bsv - this is the basic
          testbench for the switch

    TestLog:
       LOG - logfile from the test run

    Verilog:
       mkTb.v - the generated Verilog corresponding to Tb.bsv
       mkSwitch.v - the generated Verilog corresponding to Switch.bsv


v3:
    There are three directories in this directory: 

    Sources:
       Makefile - makefile for compiling the files
       Socket_IFC.bsv - this
          file holds the definitions of the interfaces, types and functions
          for the socket interface
       EdgeFIFOs.bsv - this holds a set of
          single element FIFOs for use in this version of the switch.
       Switch.bsv - this file is the source code for the switch design.
          This is the third version of the design.  It represents the second
          refinement step
       Tb.bsv - this is the basic testbench for the
          switch
 
   TestLog:
       LOG - logfile from the test run

    Verilog:
       mkTb.v - the generated Verilog corresponding to Tb.bsv
       mkSwitch.v - the generated Verilog corresponding to Switch.bsv


FinalVersion.v4:
    There are four directories in this directory:

    Sources: 
        Makefile - makefile for compiling the files
        Socket_IFC.bsv - this file holds the definitions of the
           interfaces, types and functions for the socket interface
        EdgeFIFOs.bsv - this holds the single element FIFOs leveraged
           by the switch design Switch.bsv - this file is the source code
           for the switch design.  This is the final version of the
           design.
        Tb.bsv - this is the basic testbench for the switch
        Tb1.bsv - this is a testbench that tests latency across the
           switch
        Tb2.bsv - this is a testbench that tests the
           round-robin arbitration of the switch

    TestLog:
        LOG - this is the output from the tests

    Verilog:
        mkSwitch.v - this is the Verilog code for the switch.
           This code was generated from the source files by the Bluespec
           compiler.
        mkTb.v - this is the Verilog code for the
           testbench.  This code was generated from the source files by
           the Bluespec compiler.

    DCSynthesis:
	(this directory holds all the files associated with the DC
         synthesis runs for the 2x2 switch.  There is a directory
         for the 65 nm runs and a directory for the 180 nm runs.)

AlternativeFinalVersion_in_ESESystemC.v4:
  (this directory holds an ESE SystemC version of the final implementation)

   Makefile - makefile for compiling the files
   socket_ifc.hpp - this
      file holds the definitions of the interfaces, types and functions
      for the socket interface
   edge_fifos.hpp - this holds the single
      element FIFOs leveraged by the switch design
   switch.hpp - this file
      is the source code for the switch design.  This is the final
      version of the design.
   tb1.hpp - this is the basic testbench for
      the switch
   tb2.hpp - this is a testbench that tests the round-robin
      arbitration of the switch
   tb3.hpp - this is a testbench that tests
      latency across the switch
   sys.cpp - this holds sc_main()
   sys.tb1.out - output from tb1 tests
   sys.tb2.out - output from tb2
      tests
   sys.tb3.out - output from tb3 tests




Under the directory DMA, there are four directories:


Sources:
    Makefile - makefile for compiling the files
    DMA.bsv - this is the main file for the DMA controller
    EdgeFIFOs.bsv - this holds the edge FIFOs in the design
    FIFOS.bsv - this holds the other FIFOs in the design
    Socket_IFC.bsv - this file holds the definitions of the interfaces,
       types and functions for the  socket interface
    Targets.bsv - this file holds the dummy memory module used in
       the testbench setup
    TestBench.bsv - this file holds the testbench for the DMA controller

TestLog:
    LOG - this is the output from the tests

Verilog:
    mkDMA.v - this is the Verilog code for the DMA controller.  
       This code was generated from the source files by the Bluespec compiler.
    sysTestBench.v - this is the Verilog code for the testbench.
       This code was generated from the source files by the Bluespec compiler.
    mkFifo2.v - this is the Verilog code for one of the FIFOs
       used in the design.  This code was generated from the source
       files by the Bluespec compiler.
    mkFifo4.v - this is the Verilog code for one of the FIFOs used in the
       design.  This code was generated from the source files by the
       Bluespec compiler.

DCSynthesis:
    (this directory holds all the files associated with the DC
     synthesis runs for the 2x2 switch.  There is a directory
     for the 65 nm runs and a directory for the 180 nm runs.)
