//
// Generated by Bluespec Compiler, version 2006.11 (build 9956, 2006-11-11)
// 
// On Mon Feb 12 11:59:37 EST 2007
// 
// Method conflict info:
// Method: cfg_slave_req_putReq
// Conflict-free: cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
// Conflicts: cfg_slave_req_putReq
//  
// Method: cfg_slave_req_reqAccept
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
//  
// Method: cfg_slave_resp_getRespOp
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
//  
// Method: cfg_slave_resp_getRespInfo
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
//  
// Method: cfg_slave_resp_getRespAddr
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
//  
// Method: cfg_slave_resp_getRespData
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
//  
// Method: cfg_slave_resp_respAccept
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_int,
//                               st_ch1_int,
//                               st_ch2_int,
//                               st_ch3_int,
//                               st_ch0_busy,
//                               st_ch1_busy,
//                               st_ch2_busy,
//                               st_ch3_busy
// Conflicts: cfg_slave_resp_respAccept
//  
// Method: mmu_master_req_getReqOp
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
//  
// Method: mmu_master_req_getReqInfo
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
//  
// Method: mmu_master_req_getReqAddr
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
//  
// Method: mmu_master_req_getReqData
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
//  
// Method: mmu_master_req_reqAccept
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch0_int,
//                                st_ch1_int,
//                                st_ch2_int,
//                                st_ch3_int
// Conflicts: mmu_master_req_reqAccept
//  
// Method: mmu_master_resp_putResp
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_respAccept,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch0_int,
//                                st_ch1_int,
//                                st_ch2_int,
//                                st_ch3_int
// Conflicts: mmu_master_resp_putResp
//  
// Method: mmu_master_resp_respAccept
// Conflict-free: cfg_slave_req_putReq,
//                cfg_slave_req_reqAccept,
//                cfg_slave_resp_getRespOp,
//                cfg_slave_resp_getRespInfo,
//                cfg_slave_resp_getRespAddr,
//                cfg_slave_resp_getRespData,
//                cfg_slave_resp_respAccept,
//                mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
//  
// Method: st_ch0_int
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch0_int
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch0_busy
//  
// Method: st_ch1_int
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch1_int
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch1_busy
//  
// Method: st_ch2_int
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch2_int
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch2_busy
//  
// Method: st_ch3_int
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch3_int
// Sequenced after (restricted): mmu_master_req_reqAccept,
//                               mmu_master_resp_putResp,
//                               st_ch3_busy
//  
// Method: st_ch0_busy
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch0_int
//  
// Method: st_ch1_busy
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch2_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch1_int
//  
// Method: st_ch2_busy
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch3_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch2_int
//  
// Method: st_ch3_busy
// Conflict-free: mmu_master_req_getReqOp,
//                mmu_master_req_getReqInfo,
//                mmu_master_req_getReqAddr,
//                mmu_master_req_getReqData,
//                mmu_master_req_reqAccept,
//                mmu_master_resp_putResp,
//                mmu_master_resp_respAccept,
//                st_ch0_int,
//                st_ch1_int,
//                st_ch2_int,
//                st_ch0_busy,
//                st_ch1_busy,
//                st_ch2_busy,
//                st_ch3_busy
// Sequenced before (restricted): cfg_slave_req_putReq,
//                                cfg_slave_req_reqAccept,
//                                cfg_slave_resp_getRespOp,
//                                cfg_slave_resp_getRespInfo,
//                                cfg_slave_resp_getRespAddr,
//                                cfg_slave_resp_getRespData,
//                                cfg_slave_resp_respAccept,
//                                st_ch3_int
//  
// 
// Ports:
// Name                         I/O  size props
// cfg_slave_req_reqAccept        O     1
// cfg_slave_resp_getRespOp       O     1
// cfg_slave_resp_getRespInfo     O    10
// cfg_slave_resp_getRespAddr     O     1
// cfg_slave_resp_getRespData     O    32
// mmu_master_req_getReqOp        O     2
// mmu_master_req_getReqInfo      O    10 reg
// mmu_master_req_getReqAddr      O    32 reg
// mmu_master_req_getReqData      O    32 reg
// mmu_master_resp_respAccept     O     1
// st_ch0_busy                    O     1 reg
// st_ch1_busy                    O     1 reg
// st_ch2_busy                    O     1 reg
// st_ch3_busy                    O     1 reg
// CLK                            I     1
// RST_N                          I     1
// cfg_slave_req_putReq_reqOp     I     2
// cfg_slave_req_putReq_reqInfo   I    10
// cfg_slave_req_putReq_reqAddr   I    32
// cfg_slave_req_putReq_reqData   I    32
// mmu_master_resp_putResp_respOp I     1
// mmu_master_resp_putResp_respInfo I    10
// mmu_master_resp_putResp_respAddr I     1
// mmu_master_resp_putResp_respData I    32
// EN_cfg_slave_resp_respAccept   I     1
// EN_mmu_master_req_reqAccept    I     1
// EN_st_ch0_int                  I     1
// EN_st_ch1_int                  I     1
// EN_st_ch2_int                  I     1
// EN_st_ch3_int                  I     1
// 
// No combinational paths from inputs to outputs
// 
//
//  This DMA has 4 channels, which allows it to process 4 transfers
//  simultaneously. The main difference from a 1-channel DMA is that
//  we need to create vectors (arrays) of each channel's resources.
//  Each channel will have a unique set of registers to track its
//  state.
// 
// Comments on the inlined module `mmuRespF':
//   a fifo to hold incoming responses from the memory
// 
// Comments on the inlined module `mmuReqF':
//   a fifo to hold outgoing requests towards the memory
// 
// Comments on the inlined module `cnfRespF':
//   a fifo to hold outgoing configuration responses
// 
// Comments on the inlined module `cnfReqF':
//   a fifo to hold incoming configuration requests
// 
// 

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkDMA(CLK,
             RST_N,
             
             cfg_slave_req_putReq_reqOp,
             cfg_slave_req_putReq_reqInfo,
             cfg_slave_req_putReq_reqAddr,
             cfg_slave_req_putReq_reqData,
             
             cfg_slave_req_reqAccept,
             
             cfg_slave_resp_getRespOp,
             
             cfg_slave_resp_getRespInfo,
             
             cfg_slave_resp_getRespAddr,
             
             cfg_slave_resp_getRespData,
             
             EN_cfg_slave_resp_respAccept,
             
             mmu_master_req_getReqOp,
             
             mmu_master_req_getReqInfo,
             
             mmu_master_req_getReqAddr,
             
             mmu_master_req_getReqData,
             
             EN_mmu_master_req_reqAccept,
             
             mmu_master_resp_putResp_respOp,
             mmu_master_resp_putResp_respInfo,
             mmu_master_resp_putResp_respAddr,
             mmu_master_resp_putResp_respData,
             
             mmu_master_resp_respAccept,
             
             EN_st_ch0_int,
             
             EN_st_ch1_int,
             
             EN_st_ch2_int,
             
             EN_st_ch3_int,
             
             st_ch0_busy,
             
             st_ch1_busy,
             
             st_ch2_busy,
             
             st_ch3_busy);
  input  CLK;
  input  RST_N;
  
  // action method cfg_slave_req_putReq
  input  [1 : 0] cfg_slave_req_putReq_reqOp;
  input  [9 : 0] cfg_slave_req_putReq_reqInfo;
  input  [31 : 0] cfg_slave_req_putReq_reqAddr;
  input  [31 : 0] cfg_slave_req_putReq_reqData;
  
  // value method cfg_slave_req_reqAccept
  output cfg_slave_req_reqAccept;
  
  // value method cfg_slave_resp_getRespOp
  output cfg_slave_resp_getRespOp;
  
  // value method cfg_slave_resp_getRespInfo
  output [9 : 0] cfg_slave_resp_getRespInfo;
  
  // value method cfg_slave_resp_getRespAddr
  output cfg_slave_resp_getRespAddr;
  
  // value method cfg_slave_resp_getRespData
  output [31 : 0] cfg_slave_resp_getRespData;
  
  // action method cfg_slave_resp_respAccept
  input  EN_cfg_slave_resp_respAccept;
  
  // value method mmu_master_req_getReqOp
  output [1 : 0] mmu_master_req_getReqOp;
  
  // value method mmu_master_req_getReqInfo
  output [9 : 0] mmu_master_req_getReqInfo;
  
  // value method mmu_master_req_getReqAddr
  output [31 : 0] mmu_master_req_getReqAddr;
  
  // value method mmu_master_req_getReqData
  output [31 : 0] mmu_master_req_getReqData;
  
  // action method mmu_master_req_reqAccept
  input  EN_mmu_master_req_reqAccept;
  
  // action method mmu_master_resp_putResp
  input  mmu_master_resp_putResp_respOp;
  input  [9 : 0] mmu_master_resp_putResp_respInfo;
  input  mmu_master_resp_putResp_respAddr;
  input  [31 : 0] mmu_master_resp_putResp_respData;
  
  // value method mmu_master_resp_respAccept
  output mmu_master_resp_respAccept;
  
  // action method st_ch0_int
  input  EN_st_ch0_int;
  
  // action method st_ch1_int
  input  EN_st_ch1_int;
  
  // action method st_ch2_int
  input  EN_st_ch2_int;
  
  // action method st_ch3_int
  input  EN_st_ch3_int;
  
  // value method st_ch0_busy
  output st_ch0_busy;
  
  // value method st_ch1_busy
  output st_ch1_busy;
  
  // value method st_ch2_busy
  output st_ch2_busy;
  
  // value method st_ch3_busy
  output st_ch3_busy;

  // signals for module outputs
  wire [31 : 0] cfg_slave_resp_getRespData,
                mmu_master_req_getReqAddr,
                mmu_master_req_getReqData;
  wire [9 : 0] cfg_slave_resp_getRespInfo, mmu_master_req_getReqInfo;
  wire [1 : 0] mmu_master_req_getReqOp;
  wire cfg_slave_req_reqAccept,
       cfg_slave_resp_getRespAddr,
       cfg_slave_resp_getRespOp,
       mmu_master_resp_respAccept,
       st_ch0_busy,
       st_ch1_busy,
       st_ch2_busy,
       st_ch3_busy;

  // inlined wires
  reg [75 : 0] mmuReqF_rw_enq$wget;
  wire [75 : 0] cnfReqF_rw_enq$wget;
  wire [43 : 0] mmuRespF_rw_enq$wget;
  wire cnfReqF_pw_deq$whas,
       cnfReqF_rw_enq$whas,
       cnfRespF_rw_enq$whas,
       mmuReqF_pw_deq$whas,
       mmuReqF_rw_enq$whas,
       mmuRespF_rw_enq$whas;

  // register cnfReqF_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] cnfReqF_taggedReg;
  wire [76 : 0] cnfReqF_taggedReg$D_IN;
  wire cnfReqF_taggedReg$EN;

  // register cnfRespF_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] cnfRespF_taggedReg;
  wire [44 : 0] cnfRespF_taggedReg$D_IN;
  wire cnfRespF_taggedReg$EN;

  // register currentReadRs_i
  // A counter to hold number of words already read (1 per channel)
  reg [15 : 0] currentReadRs_i;
  wire [15 : 0] currentReadRs_i$D_IN;
  wire currentReadRs_i$EN;

  // register currentReadRs_i_1
  // A counter to hold number of words already read (1 per channel)
  reg [15 : 0] currentReadRs_i_1;
  wire [15 : 0] currentReadRs_i_1$D_IN;
  wire currentReadRs_i_1$EN;

  // register currentReadRs_i_2
  // A counter to hold number of words already read (1 per channel)
  reg [15 : 0] currentReadRs_i_2;
  wire [15 : 0] currentReadRs_i_2$D_IN;
  wire currentReadRs_i_2$EN;

  // register currentReadRs_i_3
  // A counter to hold number of words already read (1 per channel)
  reg [15 : 0] currentReadRs_i_3;
  wire [15 : 0] currentReadRs_i_3$D_IN;
  wire currentReadRs_i_3$EN;

  // register currentWriteRs_i
  // A counter to hold number of words already written (1 per channel)
  reg [15 : 0] currentWriteRs_i;
  wire [15 : 0] currentWriteRs_i$D_IN;
  wire currentWriteRs_i$EN;

  // register currentWriteRs_i_1
  // A counter to hold number of words already written (1 per channel)
  reg [15 : 0] currentWriteRs_i_1;
  wire [15 : 0] currentWriteRs_i_1$D_IN;
  wire currentWriteRs_i_1$EN;

  // register currentWriteRs_i_2
  // A counter to hold number of words already written (1 per channel)
  reg [15 : 0] currentWriteRs_i_2;
  wire [15 : 0] currentWriteRs_i_2$D_IN;
  wire currentWriteRs_i_2$EN;

  // register currentWriteRs_i_3
  // A counter to hold number of words already written (1 per channel)
  reg [15 : 0] currentWriteRs_i_3;
  wire [15 : 0] currentWriteRs_i_3$D_IN;
  wire currentWriteRs_i_3$EN;

  // register destAddrRs_i
  // The destination address
  reg [31 : 0] destAddrRs_i;
  wire [31 : 0] destAddrRs_i$D_IN;
  wire destAddrRs_i$EN;

  // register destAddrRs_i_1
  // The destination address
  reg [31 : 0] destAddrRs_i_1;
  wire [31 : 0] destAddrRs_i_1$D_IN;
  wire destAddrRs_i_1$EN;

  // register destAddrRs_i_2
  // The destination address
  reg [31 : 0] destAddrRs_i_2;
  wire [31 : 0] destAddrRs_i_2$D_IN;
  wire destAddrRs_i_2$EN;

  // register destAddrRs_i_3
  // The destination address
  reg [31 : 0] destAddrRs_i_3;
  wire [31 : 0] destAddrRs_i_3$D_IN;
  wire destAddrRs_i_3$EN;

  // register dmaEnabledRs_i
  // This register indicates whether a transfer is enabled in the channel.
  reg dmaEnabledRs_i;
  reg dmaEnabledRs_i$D_IN;
  wire dmaEnabledRs_i$EN;

  // register dmaEnabledRs_i_1
  // This register indicates whether a transfer is enabled in the channel.
  reg dmaEnabledRs_i_1;
  reg dmaEnabledRs_i_1$D_IN;
  wire dmaEnabledRs_i_1$EN;

  // register dmaEnabledRs_i_2
  // This register indicates whether a transfer is enabled in the channel.
  reg dmaEnabledRs_i_2;
  reg dmaEnabledRs_i_2$D_IN;
  wire dmaEnabledRs_i_2$EN;

  // register dmaEnabledRs_i_3
  // This register indicates whether a transfer is enabled in the channel.
  reg dmaEnabledRs_i_3;
  reg dmaEnabledRs_i_3$D_IN;
  wire dmaEnabledRs_i_3$EN;

  // register mmuReqF_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] mmuReqF_taggedReg;
  wire [76 : 0] mmuReqF_taggedReg$D_IN;
  wire mmuReqF_taggedReg$EN;

  // register mmuRespF_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] mmuRespF_taggedReg;
  wire [44 : 0] mmuRespF_taggedReg$D_IN;
  wire mmuRespF_taggedReg$EN;

  // register readAddrRs_i
  // A register to hold the read address (1 per channel)
  reg [31 : 0] readAddrRs_i;
  wire [31 : 0] readAddrRs_i$D_IN;
  wire readAddrRs_i$EN;

  // register readAddrRs_i_1
  // A register to hold the read address (1 per channel)
  reg [31 : 0] readAddrRs_i_1;
  wire [31 : 0] readAddrRs_i_1$D_IN;
  wire readAddrRs_i_1$EN;

  // register readAddrRs_i_2
  // A register to hold the read address (1 per channel)
  reg [31 : 0] readAddrRs_i_2;
  wire [31 : 0] readAddrRs_i_2$D_IN;
  wire readAddrRs_i_2$EN;

  // register readAddrRs_i_3
  // A register to hold the read address (1 per channel)
  reg [31 : 0] readAddrRs_i_3;
  wire [31 : 0] readAddrRs_i_3$D_IN;
  wire readAddrRs_i_3$EN;

  // register readCntrRs_i
  // A register for the number of data-words to be transferred (1 per channel)
  reg [15 : 0] readCntrRs_i;
  wire [15 : 0] readCntrRs_i$D_IN;
  wire readCntrRs_i$EN;

  // register readCntrRs_i_1
  // A register for the number of data-words to be transferred (1 per channel)
  reg [15 : 0] readCntrRs_i_1;
  wire [15 : 0] readCntrRs_i_1$D_IN;
  wire readCntrRs_i_1$EN;

  // register readCntrRs_i_2
  // A register for the number of data-words to be transferred (1 per channel)
  reg [15 : 0] readCntrRs_i_2;
  wire [15 : 0] readCntrRs_i_2$D_IN;
  wire readCntrRs_i_2$EN;

  // register readCntrRs_i_3
  // A register for the number of data-words to be transferred (1 per channel)
  reg [15 : 0] readCntrRs_i_3;
  wire [15 : 0] readCntrRs_i_3$D_IN;
  wire readCntrRs_i_3$EN;

  // submodule destAddrFs_i
  //  We also want to pass the destination address for each read over
  //  to the write side
  //  The depth of this fifo limits the number of outstanding reads
  //  which may be pending before the write.  The maximun outstanding
  //  reads depends on the overall latency of the read requests.
  wire [31 : 0] destAddrFs_i$enq_x1, destAddrFs_i$first;
  wire destAddrFs_i$EN_clear,
       destAddrFs_i$EN_deq,
       destAddrFs_i$EN_enq,
       destAddrFs_i$RDY_deq,
       destAddrFs_i$RDY_enq,
       destAddrFs_i$RDY_first;
  mkFifo4 destAddrFs_i(.CLK(CLK),
                       .RST_N(RST_N),
                       .enq_x1(destAddrFs_i$enq_x1),
                       .EN_enq(destAddrFs_i$EN_enq),
                       .EN_deq(destAddrFs_i$EN_deq),
                       .EN_clear(destAddrFs_i$EN_clear),
                       .RDY_enq(destAddrFs_i$RDY_enq),
                       .RDY_deq(destAddrFs_i$RDY_deq),
                       .first(destAddrFs_i$first),
                       .RDY_first(destAddrFs_i$RDY_first),
                       .RDY_clear());

  // submodule destAddrFs_i_1
  //  We also want to pass the destination address for each read over
  //  to the write side
  //  The depth of this fifo limits the number of outstanding reads
  //  which may be pending before the write.  The maximun outstanding
  //  reads depends on the overall latency of the read requests.
  wire [31 : 0] destAddrFs_i_1$enq_x1, destAddrFs_i_1$first;
  wire destAddrFs_i_1$EN_clear,
       destAddrFs_i_1$EN_deq,
       destAddrFs_i_1$EN_enq,
       destAddrFs_i_1$RDY_deq,
       destAddrFs_i_1$RDY_enq,
       destAddrFs_i_1$RDY_first;
  mkFifo4 destAddrFs_i_1(.CLK(CLK),
                         .RST_N(RST_N),
                         .enq_x1(destAddrFs_i_1$enq_x1),
                         .EN_enq(destAddrFs_i_1$EN_enq),
                         .EN_deq(destAddrFs_i_1$EN_deq),
                         .EN_clear(destAddrFs_i_1$EN_clear),
                         .RDY_enq(destAddrFs_i_1$RDY_enq),
                         .RDY_deq(destAddrFs_i_1$RDY_deq),
                         .first(destAddrFs_i_1$first),
                         .RDY_first(destAddrFs_i_1$RDY_first),
                         .RDY_clear());

  // submodule destAddrFs_i_2
  //  We also want to pass the destination address for each read over
  //  to the write side
  //  The depth of this fifo limits the number of outstanding reads
  //  which may be pending before the write.  The maximun outstanding
  //  reads depends on the overall latency of the read requests.
  wire [31 : 0] destAddrFs_i_2$enq_x1, destAddrFs_i_2$first;
  wire destAddrFs_i_2$EN_clear,
       destAddrFs_i_2$EN_deq,
       destAddrFs_i_2$EN_enq,
       destAddrFs_i_2$RDY_deq,
       destAddrFs_i_2$RDY_enq,
       destAddrFs_i_2$RDY_first;
  mkFifo4 destAddrFs_i_2(.CLK(CLK),
                         .RST_N(RST_N),
                         .enq_x1(destAddrFs_i_2$enq_x1),
                         .EN_enq(destAddrFs_i_2$EN_enq),
                         .EN_deq(destAddrFs_i_2$EN_deq),
                         .EN_clear(destAddrFs_i_2$EN_clear),
                         .RDY_enq(destAddrFs_i_2$RDY_enq),
                         .RDY_deq(destAddrFs_i_2$RDY_deq),
                         .first(destAddrFs_i_2$first),
                         .RDY_first(destAddrFs_i_2$RDY_first),
                         .RDY_clear());

  // submodule destAddrFs_i_3
  //  We also want to pass the destination address for each read over
  //  to the write side
  //  The depth of this fifo limits the number of outstanding reads
  //  which may be pending before the write.  The maximun outstanding
  //  reads depends on the overall latency of the read requests.
  wire [31 : 0] destAddrFs_i_3$enq_x1, destAddrFs_i_3$first;
  wire destAddrFs_i_3$EN_clear,
       destAddrFs_i_3$EN_deq,
       destAddrFs_i_3$EN_enq,
       destAddrFs_i_3$RDY_deq,
       destAddrFs_i_3$RDY_enq,
       destAddrFs_i_3$RDY_first;
  mkFifo4 destAddrFs_i_3(.CLK(CLK),
                         .RST_N(RST_N),
                         .enq_x1(destAddrFs_i_3$enq_x1),
                         .EN_enq(destAddrFs_i_3$EN_enq),
                         .EN_deq(destAddrFs_i_3$EN_deq),
                         .EN_clear(destAddrFs_i_3$EN_clear),
                         .RDY_enq(destAddrFs_i_3$RDY_enq),
                         .RDY_deq(destAddrFs_i_3$RDY_deq),
                         .first(destAddrFs_i_3$first),
                         .RDY_first(destAddrFs_i_3$RDY_first),
                         .RDY_clear());

  // submodule responseDataFs_i
  //  a FIFO to pass the read response to the write side
  //  thus allowing pending transations and concurrency
  wire [31 : 0] responseDataFs_i$enq_x1, responseDataFs_i$first;
  wire responseDataFs_i$EN_clear,
       responseDataFs_i$EN_deq,
       responseDataFs_i$EN_enq,
       responseDataFs_i$RDY_deq,
       responseDataFs_i$RDY_enq,
       responseDataFs_i$RDY_first;
  mkFifo2 responseDataFs_i(.CLK(CLK),
                           .RST_N(RST_N),
                           .enq_x1(responseDataFs_i$enq_x1),
                           .EN_enq(responseDataFs_i$EN_enq),
                           .EN_deq(responseDataFs_i$EN_deq),
                           .EN_clear(responseDataFs_i$EN_clear),
                           .RDY_enq(responseDataFs_i$RDY_enq),
                           .RDY_deq(responseDataFs_i$RDY_deq),
                           .first(responseDataFs_i$first),
                           .RDY_first(responseDataFs_i$RDY_first),
                           .RDY_clear());

  // submodule responseDataFs_i_1
  //  a FIFO to pass the read response to the write side
  //  thus allowing pending transations and concurrency
  wire [31 : 0] responseDataFs_i_1$enq_x1, responseDataFs_i_1$first;
  wire responseDataFs_i_1$EN_clear,
       responseDataFs_i_1$EN_deq,
       responseDataFs_i_1$EN_enq,
       responseDataFs_i_1$RDY_deq,
       responseDataFs_i_1$RDY_enq,
       responseDataFs_i_1$RDY_first;
  mkFifo2 responseDataFs_i_1(.CLK(CLK),
                             .RST_N(RST_N),
                             .enq_x1(responseDataFs_i_1$enq_x1),
                             .EN_enq(responseDataFs_i_1$EN_enq),
                             .EN_deq(responseDataFs_i_1$EN_deq),
                             .EN_clear(responseDataFs_i_1$EN_clear),
                             .RDY_enq(responseDataFs_i_1$RDY_enq),
                             .RDY_deq(responseDataFs_i_1$RDY_deq),
                             .first(responseDataFs_i_1$first),
                             .RDY_first(responseDataFs_i_1$RDY_first),
                             .RDY_clear());

  // submodule responseDataFs_i_2
  //  a FIFO to pass the read response to the write side
  //  thus allowing pending transations and concurrency
  wire [31 : 0] responseDataFs_i_2$enq_x1, responseDataFs_i_2$first;
  wire responseDataFs_i_2$EN_clear,
       responseDataFs_i_2$EN_deq,
       responseDataFs_i_2$EN_enq,
       responseDataFs_i_2$RDY_deq,
       responseDataFs_i_2$RDY_enq,
       responseDataFs_i_2$RDY_first;
  mkFifo2 responseDataFs_i_2(.CLK(CLK),
                             .RST_N(RST_N),
                             .enq_x1(responseDataFs_i_2$enq_x1),
                             .EN_enq(responseDataFs_i_2$EN_enq),
                             .EN_deq(responseDataFs_i_2$EN_deq),
                             .EN_clear(responseDataFs_i_2$EN_clear),
                             .RDY_enq(responseDataFs_i_2$RDY_enq),
                             .RDY_deq(responseDataFs_i_2$RDY_deq),
                             .first(responseDataFs_i_2$first),
                             .RDY_first(responseDataFs_i_2$RDY_first),
                             .RDY_clear());

  // submodule responseDataFs_i_3
  //  a FIFO to pass the read response to the write side
  //  thus allowing pending transations and concurrency
  wire [31 : 0] responseDataFs_i_3$enq_x1, responseDataFs_i_3$first;
  wire responseDataFs_i_3$EN_clear,
       responseDataFs_i_3$EN_deq,
       responseDataFs_i_3$EN_enq,
       responseDataFs_i_3$RDY_deq,
       responseDataFs_i_3$RDY_enq,
       responseDataFs_i_3$RDY_first;
  mkFifo2 responseDataFs_i_3(.CLK(CLK),
                             .RST_N(RST_N),
                             .enq_x1(responseDataFs_i_3$enq_x1),
                             .EN_enq(responseDataFs_i_3$EN_enq),
                             .EN_deq(responseDataFs_i_3$EN_deq),
                             .EN_clear(responseDataFs_i_3$EN_clear),
                             .RDY_enq(responseDataFs_i_3$RDY_enq),
                             .RDY_deq(responseDataFs_i_3$RDY_deq),
                             .first(responseDataFs_i_3$first),
                             .RDY_first(responseDataFs_i_3$RDY_first),
                             .RDY_clear());

  // rule scheduling signals
  wire CAN_FIRE_RL_cnfReqF_rule_update_final,
       CAN_FIRE_RL_cnfRespF_rule_deq,
       CAN_FIRE_RL_cnfRespF_rule_enq,
       CAN_FIRE_RL_finishRead,
       CAN_FIRE_RL_finishRead_1,
       CAN_FIRE_RL_finishRead_2,
       CAN_FIRE_RL_finishRead_3,
       CAN_FIRE_RL_finishWrite,
       CAN_FIRE_RL_finishWrite_1,
       CAN_FIRE_RL_finishWrite_2,
       CAN_FIRE_RL_finishWrite_3,
       CAN_FIRE_RL_markTransferDone,
       CAN_FIRE_RL_markTransferDone_1,
       CAN_FIRE_RL_markTransferDone_2,
       CAN_FIRE_RL_markTransferDone_3,
       CAN_FIRE_RL_mmuReqF_rule_update_final,
       CAN_FIRE_RL_mmuRespF_rule_deq,
       CAN_FIRE_RL_mmuRespF_rule_enq,
       CAN_FIRE_RL_readConfig,
       CAN_FIRE_RL_startRead,
       CAN_FIRE_RL_startRead_1,
       CAN_FIRE_RL_startRead_2,
       CAN_FIRE_RL_startRead_3,
       CAN_FIRE_RL_startWrite,
       CAN_FIRE_RL_startWrite_1,
       CAN_FIRE_RL_startWrite_2,
       CAN_FIRE_RL_startWrite_3,
       CAN_FIRE_RL_unknownConfig,
       CAN_FIRE_RL_writeConfig,
       CAN_FIRE_cfg_slave_req_putReq,
       CAN_FIRE_cfg_slave_resp_respAccept,
       CAN_FIRE_mmu_master_req_reqAccept,
       CAN_FIRE_mmu_master_resp_putResp,
       CAN_FIRE_st_ch0_int,
       CAN_FIRE_st_ch1_int,
       CAN_FIRE_st_ch2_int,
       CAN_FIRE_st_ch3_int,
       WILL_FIRE_RL_cnfReqF_rule_update_final,
       WILL_FIRE_RL_cnfRespF_rule_deq,
       WILL_FIRE_RL_cnfRespF_rule_enq,
       WILL_FIRE_RL_finishRead,
       WILL_FIRE_RL_finishRead_1,
       WILL_FIRE_RL_finishRead_2,
       WILL_FIRE_RL_finishRead_3,
       WILL_FIRE_RL_finishWrite,
       WILL_FIRE_RL_finishWrite_1,
       WILL_FIRE_RL_finishWrite_2,
       WILL_FIRE_RL_finishWrite_3,
       WILL_FIRE_RL_markTransferDone,
       WILL_FIRE_RL_markTransferDone_1,
       WILL_FIRE_RL_markTransferDone_2,
       WILL_FIRE_RL_markTransferDone_3,
       WILL_FIRE_RL_mmuReqF_rule_update_final,
       WILL_FIRE_RL_mmuRespF_rule_deq,
       WILL_FIRE_RL_mmuRespF_rule_enq,
       WILL_FIRE_RL_readConfig,
       WILL_FIRE_RL_startRead,
       WILL_FIRE_RL_startRead_1,
       WILL_FIRE_RL_startRead_2,
       WILL_FIRE_RL_startRead_3,
       WILL_FIRE_RL_startWrite,
       WILL_FIRE_RL_startWrite_1,
       WILL_FIRE_RL_startWrite_2,
       WILL_FIRE_RL_startWrite_3,
       WILL_FIRE_RL_unknownConfig,
       WILL_FIRE_RL_writeConfig,
       WILL_FIRE_cfg_slave_req_putReq,
       WILL_FIRE_cfg_slave_resp_respAccept,
       WILL_FIRE_mmu_master_req_reqAccept,
       WILL_FIRE_mmu_master_resp_putResp,
       WILL_FIRE_st_ch0_int,
       WILL_FIRE_st_ch1_int,
       WILL_FIRE_st_ch2_int,
       WILL_FIRE_st_ch3_int;

  // inputs to muxes for submodule ports
  wire [75 : 0] MUX_mmuReqF_rw_enq$wset_1__VAL_1,
                MUX_mmuReqF_rw_enq$wset_1__VAL_2,
                MUX_mmuReqF_rw_enq$wset_1__VAL_3,
                MUX_mmuReqF_rw_enq$wset_1__VAL_4,
                MUX_mmuReqF_rw_enq$wset_1__VAL_5,
                MUX_mmuReqF_rw_enq$wset_1__VAL_6,
                MUX_mmuReqF_rw_enq$wset_1__VAL_7,
                MUX_mmuReqF_rw_enq$wset_1__VAL_8;
  wire [44 : 0] MUX_cnfRespF_taggedReg$write_1__VAL_1,
                MUX_mmuRespF_taggedReg$write_1__VAL_1;
  wire [43 : 0] MUX_cnfRespF_rw_enq$wset_1__VAL_1,
                MUX_cnfRespF_rw_enq$wset_1__VAL_2,
                MUX_cnfRespF_rw_enq$wset_1__VAL_3;
  wire [31 : 0] MUX_destAddrRs_i$write_1__VAL_2,
                MUX_destAddrRs_i_1$write_1__VAL_2,
                MUX_destAddrRs_i_2$write_1__VAL_2,
                MUX_destAddrRs_i_3$write_1__VAL_2,
                MUX_readAddrRs_i$write_1__VAL_2,
                MUX_readAddrRs_i_1$write_1__VAL_2,
                MUX_readAddrRs_i_2$write_1__VAL_2,
                MUX_readAddrRs_i_3$write_1__VAL_2;
  wire [15 : 0] MUX_currentReadRs_i$write_1__VAL_1,
                MUX_currentReadRs_i_1$write_1__VAL_1,
                MUX_currentReadRs_i_2$write_1__VAL_1,
                MUX_currentReadRs_i_3$write_1__VAL_1,
                MUX_currentWriteRs_i$write_1__VAL_1,
                MUX_currentWriteRs_i_1$write_1__VAL_1,
                MUX_currentWriteRs_i_2$write_1__VAL_1,
                MUX_currentWriteRs_i_3$write_1__VAL_1;
  wire MUX_destAddrRs_i$write_1__SEL_1,
       MUX_destAddrRs_i_1$write_1__SEL_1,
       MUX_destAddrRs_i_2$write_1__SEL_1,
       MUX_destAddrRs_i_3$write_1__SEL_1,
       MUX_dmaEnabledRs_i$write_1__SEL_1,
       MUX_dmaEnabledRs_i_1$write_1__SEL_1,
       MUX_dmaEnabledRs_i_2$write_1__SEL_1,
       MUX_dmaEnabledRs_i_3$write_1__SEL_1,
       MUX_readAddrRs_i$write_1__SEL_1,
       MUX_readAddrRs_i_1$write_1__SEL_1,
       MUX_readAddrRs_i_2$write_1__SEL_1,
       MUX_readAddrRs_i_3$write_1__SEL_1;

  // remaining internal signals
  reg [43 : 0] _x__h347;
  reg [31 : 0] CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1,
               PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2,
               resp_respData__h6263;
  reg [15 : 0] x__h6559;
  reg x__h6411;
  wire [9 : 0] IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301;

  // action method cfg_slave_req_putReq
  assign CAN_FIRE_cfg_slave_req_putReq = 1'd1 ;
  assign WILL_FIRE_cfg_slave_req_putReq = 1'b1 ;

  // value method cfg_slave_req_reqAccept
  assign cfg_slave_req_reqAccept =
             !cnfReqF_taggedReg[76] || cnfReqF_pw_deq$whas ;

  // value method cfg_slave_resp_getRespOp
  assign cfg_slave_resp_getRespOp =
             (cnfRespF_taggedReg[44] || cnfRespF_rw_enq$whas) &&
             (cnfRespF_rw_enq$whas ? _x__h347[43] : cnfRespF_taggedReg[43]) ;

  // value method cfg_slave_resp_getRespInfo
  assign cfg_slave_resp_getRespInfo =
             cnfRespF_rw_enq$whas ?
               _x__h347[42:33] :
               cnfRespF_taggedReg[42:33] ;

  // value method cfg_slave_resp_getRespAddr
  assign cfg_slave_resp_getRespAddr =
             cnfRespF_rw_enq$whas ? _x__h347[32] : cnfRespF_taggedReg[32] ;

  // value method cfg_slave_resp_getRespData
  assign cfg_slave_resp_getRespData =
             cnfRespF_rw_enq$whas ?
               _x__h347[31:0] :
               cnfRespF_taggedReg[31:0] ;

  // action method cfg_slave_resp_respAccept
  assign CAN_FIRE_cfg_slave_resp_respAccept = 1'd1 ;
  assign WILL_FIRE_cfg_slave_resp_respAccept = EN_cfg_slave_resp_respAccept ;

  // value method mmu_master_req_getReqOp
  assign mmu_master_req_getReqOp =
             mmuReqF_taggedReg[76] ? mmuReqF_taggedReg[75:74] : 2'd0 ;

  // value method mmu_master_req_getReqInfo
  assign mmu_master_req_getReqInfo = mmuReqF_taggedReg[73:64] ;

  // value method mmu_master_req_getReqAddr
  assign mmu_master_req_getReqAddr = mmuReqF_taggedReg[63:32] ;

  // value method mmu_master_req_getReqData
  assign mmu_master_req_getReqData = mmuReqF_taggedReg[31:0] ;

  // action method mmu_master_req_reqAccept
  assign CAN_FIRE_mmu_master_req_reqAccept = 1'd1 ;
  assign WILL_FIRE_mmu_master_req_reqAccept = EN_mmu_master_req_reqAccept ;

  // action method mmu_master_resp_putResp
  assign CAN_FIRE_mmu_master_resp_putResp = 1'd1 ;
  assign WILL_FIRE_mmu_master_resp_putResp = 1'b1 ;

  // value method mmu_master_resp_respAccept
  assign mmu_master_resp_respAccept = !mmuRespF_taggedReg[44] ;

  // action method st_ch0_int
  assign CAN_FIRE_st_ch0_int = 1'd1 ;
  assign WILL_FIRE_st_ch0_int = EN_st_ch0_int ;

  // action method st_ch1_int
  assign CAN_FIRE_st_ch1_int = 1'd1 ;
  assign WILL_FIRE_st_ch1_int = EN_st_ch1_int ;

  // action method st_ch2_int
  assign CAN_FIRE_st_ch2_int = 1'd1 ;
  assign WILL_FIRE_st_ch2_int = EN_st_ch2_int ;

  // action method st_ch3_int
  assign CAN_FIRE_st_ch3_int = 1'd1 ;
  assign WILL_FIRE_st_ch3_int = EN_st_ch3_int ;

  // value method st_ch0_busy
  assign st_ch0_busy = dmaEnabledRs_i ;

  // value method st_ch1_busy
  assign st_ch1_busy = dmaEnabledRs_i_1 ;

  // value method st_ch2_busy
  assign st_ch2_busy = dmaEnabledRs_i_2 ;

  // value method st_ch3_busy
  assign st_ch3_busy = dmaEnabledRs_i_3 ;

  // rule RL_startWrite
  //    This rule starts a write process
  //    Note that this rule conflicts with rule 
  //    startRead, so we make this rule more urgent.
  //    I.e., finish writing before you start
  //    reading more.
  assign CAN_FIRE_RL_startWrite =
             responseDataFs_i$RDY_first && destAddrFs_i$RDY_first &&
             responseDataFs_i$RDY_deq && destAddrFs_i$RDY_deq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) ;
  assign WILL_FIRE_RL_startWrite = CAN_FIRE_RL_startWrite ;

  // rule RL_startWrite_1
  //    This rule starts a write process
  //    Note that this rule conflicts with rule 
  //    startRead, so we make this rule more urgent.
  //    I.e., finish writing before you start
  //    reading more.
  assign CAN_FIRE_RL_startWrite_1 =
             responseDataFs_i_1$RDY_first && destAddrFs_i_1$RDY_first &&
             responseDataFs_i_1$RDY_deq && destAddrFs_i_1$RDY_deq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) ;
  assign WILL_FIRE_RL_startWrite_1 =
             CAN_FIRE_RL_startWrite_1 && !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_startWrite_2
  //    This rule starts a write process
  //    Note that this rule conflicts with rule 
  //    startRead, so we make this rule more urgent.
  //    I.e., finish writing before you start
  //    reading more.
  assign CAN_FIRE_RL_startWrite_2 =
             responseDataFs_i_2$RDY_first && destAddrFs_i_2$RDY_first &&
             responseDataFs_i_2$RDY_deq && destAddrFs_i_2$RDY_deq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) ;
  assign WILL_FIRE_RL_startWrite_2 =
             CAN_FIRE_RL_startWrite_2 && !WILL_FIRE_RL_startRead_1 &&
             !WILL_FIRE_RL_startWrite_1 &&
             !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_startWrite_3
  //    This rule starts a write process
  //    Note that this rule conflicts with rule 
  //    startRead, so we make this rule more urgent.
  //    I.e., finish writing before you start
  //    reading more.
  assign CAN_FIRE_RL_startWrite_3 =
             responseDataFs_i_3$RDY_first && destAddrFs_i_3$RDY_first &&
             responseDataFs_i_3$RDY_deq && destAddrFs_i_3$RDY_deq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) ;
  assign WILL_FIRE_RL_startWrite_3 =
             CAN_FIRE_RL_startWrite_3 && !WILL_FIRE_RL_startRead_2 &&
             !WILL_FIRE_RL_startWrite_2 &&
             !WILL_FIRE_RL_startRead_1 &&
             !WILL_FIRE_RL_startWrite_1 &&
             !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_readConfig
  //    A rule for reading a configuration register
  //    and generating a response.
  assign CAN_FIRE_RL_readConfig =
             cnfReqF_taggedReg[76] && !cnfRespF_taggedReg[44] &&
             cnfReqF_taggedReg[75:74] == 2'd2 ;
  assign WILL_FIRE_RL_readConfig = CAN_FIRE_RL_readConfig ;

  // rule RL_unknownConfig
  //    this is basically what's left for NOP command
  assign CAN_FIRE_RL_unknownConfig =
             cnfReqF_taggedReg[76] && !cnfRespF_taggedReg[44] ;
  assign WILL_FIRE_RL_unknownConfig =
             CAN_FIRE_RL_unknownConfig && !WILL_FIRE_RL_readConfig &&
             !WILL_FIRE_RL_writeConfig ;

  // rule RL_startRead_3
  //    This starts a read, when the dma is enabled and there
  //    are data to move (and we are in the right state)
  assign CAN_FIRE_RL_startRead_3 =
             destAddrFs_i_3$RDY_enq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) &&
             dmaEnabledRs_i_3 &&
             readCntrRs_i_3 > currentReadRs_i_3 ;
  assign WILL_FIRE_RL_startRead_3 =
             CAN_FIRE_RL_startRead_3 && !WILL_FIRE_RL_startWrite_3 &&
             !WILL_FIRE_RL_startRead_2 &&
             !WILL_FIRE_RL_startWrite_2 &&
             !WILL_FIRE_RL_startRead_1 &&
             !WILL_FIRE_RL_startWrite_1 &&
             !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_markTransferDone_3
  //    Conditions to mark when transfer is done
  assign CAN_FIRE_RL_markTransferDone_3 =
             dmaEnabledRs_i_3 && currentWriteRs_i_3 == readCntrRs_i_3 &&
             currentReadRs_i_3 == readCntrRs_i_3 ;
  assign WILL_FIRE_RL_markTransferDone_3 =
             CAN_FIRE_RL_markTransferDone_3 && !WILL_FIRE_RL_finishWrite_3 ;

  // rule RL_startRead_2
  //    This starts a read, when the dma is enabled and there
  //    are data to move (and we are in the right state)
  assign CAN_FIRE_RL_startRead_2 =
             destAddrFs_i_2$RDY_enq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) &&
             dmaEnabledRs_i_2 &&
             readCntrRs_i_2 > currentReadRs_i_2 ;
  assign WILL_FIRE_RL_startRead_2 =
             CAN_FIRE_RL_startRead_2 && !WILL_FIRE_RL_startWrite_2 &&
             !WILL_FIRE_RL_startRead_1 &&
             !WILL_FIRE_RL_startWrite_1 &&
             !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_markTransferDone_2
  //    Conditions to mark when transfer is done
  assign CAN_FIRE_RL_markTransferDone_2 =
             dmaEnabledRs_i_2 && currentWriteRs_i_2 == readCntrRs_i_2 &&
             currentReadRs_i_2 == readCntrRs_i_2 ;
  assign WILL_FIRE_RL_markTransferDone_2 =
             CAN_FIRE_RL_markTransferDone_2 && !WILL_FIRE_RL_finishWrite_2 ;

  // rule RL_startRead_1
  //    This starts a read, when the dma is enabled and there
  //    are data to move (and we are in the right state)
  assign CAN_FIRE_RL_startRead_1 =
             destAddrFs_i_1$RDY_enq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) &&
             dmaEnabledRs_i_1 &&
             readCntrRs_i_1 > currentReadRs_i_1 ;
  assign WILL_FIRE_RL_startRead_1 =
             CAN_FIRE_RL_startRead_1 && !WILL_FIRE_RL_startWrite_1 &&
             !WILL_FIRE_RL_startRead &&
             !WILL_FIRE_RL_startWrite ;

  // rule RL_markTransferDone_1
  //    Conditions to mark when transfer is done
  assign CAN_FIRE_RL_markTransferDone_1 =
             dmaEnabledRs_i_1 && currentWriteRs_i_1 == readCntrRs_i_1 &&
             currentReadRs_i_1 == readCntrRs_i_1 ;
  assign WILL_FIRE_RL_markTransferDone_1 =
             CAN_FIRE_RL_markTransferDone_1 && !WILL_FIRE_RL_finishWrite_1 ;

  // rule RL_startRead
  //    This starts a read, when the dma is enabled and there
  //    are data to move (and we are in the right state)
  assign CAN_FIRE_RL_startRead =
             destAddrFs_i$RDY_enq &&
             (!mmuReqF_taggedReg[76] || mmuReqF_pw_deq$whas) &&
             dmaEnabledRs_i &&
             readCntrRs_i > currentReadRs_i ;
  assign WILL_FIRE_RL_startRead =
             CAN_FIRE_RL_startRead && !WILL_FIRE_RL_startWrite ;

  // rule RL_markTransferDone
  //    Conditions to mark when transfer is done
  assign CAN_FIRE_RL_markTransferDone =
             dmaEnabledRs_i && currentWriteRs_i == readCntrRs_i &&
             currentReadRs_i == readCntrRs_i ;
  assign WILL_FIRE_RL_markTransferDone =
             CAN_FIRE_RL_markTransferDone && !WILL_FIRE_RL_finishWrite ;

  // rule RL_writeConfig
  //    A rule for writing to a configuration register and
  //    and generating a response.
  assign CAN_FIRE_RL_writeConfig =
             cnfReqF_taggedReg[76] && !cnfRespF_taggedReg[44] &&
             cnfReqF_taggedReg[75:74] == 2'd1 ;
  assign WILL_FIRE_RL_writeConfig = CAN_FIRE_RL_writeConfig ;

  // rule RL_finishWrite
  //    This rule waits for the write to finish
  assign CAN_FIRE_RL_finishWrite =
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd1 ;
  assign WILL_FIRE_RL_finishWrite = CAN_FIRE_RL_finishWrite ;

  // rule RL_finishRead
  //    We finish a read when we see the correct respInfo on the mmu
  //    response fifo.
  assign CAN_FIRE_RL_finishRead =
             responseDataFs_i$RDY_enq &&
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd0 ;
  assign WILL_FIRE_RL_finishRead =
             CAN_FIRE_RL_finishRead && !WILL_FIRE_RL_startWrite ;

  // rule RL_finishWrite_1
  //    This rule waits for the write to finish
  assign CAN_FIRE_RL_finishWrite_1 =
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd3 ;
  assign WILL_FIRE_RL_finishWrite_1 = CAN_FIRE_RL_finishWrite_1 ;

  // rule RL_finishRead_1
  //    We finish a read when we see the correct respInfo on the mmu
  //    response fifo.
  assign CAN_FIRE_RL_finishRead_1 =
             responseDataFs_i_1$RDY_enq &&
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd2 ;
  assign WILL_FIRE_RL_finishRead_1 =
             CAN_FIRE_RL_finishRead_1 && !WILL_FIRE_RL_startWrite_1 ;

  // rule RL_finishWrite_2
  //    This rule waits for the write to finish
  assign CAN_FIRE_RL_finishWrite_2 =
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd5 ;
  assign WILL_FIRE_RL_finishWrite_2 = CAN_FIRE_RL_finishWrite_2 ;

  // rule RL_finishRead_2
  //    We finish a read when we see the correct respInfo on the mmu
  //    response fifo.
  assign CAN_FIRE_RL_finishRead_2 =
             responseDataFs_i_2$RDY_enq &&
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd4 ;
  assign WILL_FIRE_RL_finishRead_2 =
             CAN_FIRE_RL_finishRead_2 && !WILL_FIRE_RL_startWrite_2 ;

  // rule RL_finishWrite_3
  //    This rule waits for the write to finish
  assign CAN_FIRE_RL_finishWrite_3 =
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd7 ;
  assign WILL_FIRE_RL_finishWrite_3 = CAN_FIRE_RL_finishWrite_3 ;

  // rule RL_finishRead_3
  //    We finish a read when we see the correct respInfo on the mmu
  //    response fifo.
  assign CAN_FIRE_RL_finishRead_3 =
             responseDataFs_i_3$RDY_enq &&
             (mmuRespF_taggedReg[44] || mmuRespF_rw_enq$whas) &&
             IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 ==
             10'd6 ;
  assign WILL_FIRE_RL_finishRead_3 =
             CAN_FIRE_RL_finishRead_3 && !WILL_FIRE_RL_startWrite_3 ;

  // rule RL_mmuRespF_rule_deq
  assign CAN_FIRE_RL_mmuRespF_rule_deq =
             WILL_FIRE_RL_finishWrite || WILL_FIRE_RL_finishRead ||
             WILL_FIRE_RL_finishWrite_1 ||
             WILL_FIRE_RL_finishRead_1 ||
             WILL_FIRE_RL_finishWrite_2 ||
             WILL_FIRE_RL_finishRead_2 ||
             WILL_FIRE_RL_finishWrite_3 ||
             WILL_FIRE_RL_finishRead_3 ;
  assign WILL_FIRE_RL_mmuRespF_rule_deq = CAN_FIRE_RL_mmuRespF_rule_deq ;

  // rule RL_mmuRespF_rule_enq
  assign CAN_FIRE_RL_mmuRespF_rule_enq =
             mmuRespF_rw_enq$whas && !CAN_FIRE_RL_mmuRespF_rule_deq ;
  assign WILL_FIRE_RL_mmuRespF_rule_enq = CAN_FIRE_RL_mmuRespF_rule_enq ;

  // rule RL_mmuReqF_rule_update_final
  assign CAN_FIRE_RL_mmuReqF_rule_update_final =
             mmuReqF_rw_enq$whas || mmuReqF_pw_deq$whas ;
  assign WILL_FIRE_RL_mmuReqF_rule_update_final =
             CAN_FIRE_RL_mmuReqF_rule_update_final ;

  // rule RL_cnfRespF_rule_deq
  assign CAN_FIRE_RL_cnfRespF_rule_deq =
             EN_cfg_slave_resp_respAccept &&
             (cnfRespF_taggedReg[44] || cnfRespF_rw_enq$whas) ;
  assign WILL_FIRE_RL_cnfRespF_rule_deq = CAN_FIRE_RL_cnfRespF_rule_deq ;

  // rule RL_cnfRespF_rule_enq
  assign CAN_FIRE_RL_cnfRespF_rule_enq =
             cnfRespF_rw_enq$whas && !CAN_FIRE_RL_cnfRespF_rule_deq ;
  assign WILL_FIRE_RL_cnfRespF_rule_enq = CAN_FIRE_RL_cnfRespF_rule_enq ;

  // rule RL_cnfReqF_rule_update_final
  assign CAN_FIRE_RL_cnfReqF_rule_update_final =
             cnfReqF_rw_enq$whas || cnfReqF_pw_deq$whas ;
  assign WILL_FIRE_RL_cnfReqF_rule_update_final =
             CAN_FIRE_RL_cnfReqF_rule_update_final ;

  // inputs to muxes for submodule ports
  assign MUX_destAddrRs_i$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd0 ;
  assign MUX_destAddrRs_i_1$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd1 ;
  assign MUX_destAddrRs_i_2$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd2 ;
  assign MUX_destAddrRs_i_3$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ;
  assign MUX_dmaEnabledRs_i$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd0 ;
  assign MUX_dmaEnabledRs_i_1$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd1 ;
  assign MUX_dmaEnabledRs_i_2$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd2 ;
  assign MUX_dmaEnabledRs_i_3$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ;
  assign MUX_readAddrRs_i$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd0 ;
  assign MUX_readAddrRs_i_1$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd1 ;
  assign MUX_readAddrRs_i_2$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd2 ;
  assign MUX_readAddrRs_i_3$write_1__SEL_1 =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ;
  assign MUX_cnfRespF_rw_enq$wset_1__VAL_1 =
             { 1'd1, cnfReqF_taggedReg[73:64], 1'd0, resp_respData__h6263 } ;
  assign MUX_cnfRespF_rw_enq$wset_1__VAL_2 =
             { 1'd1,
               cnfReqF_taggedReg[73:64],
               1'd0,
               cnfReqF_taggedReg[31:0] } ;
  assign MUX_cnfRespF_rw_enq$wset_1__VAL_3 =
             { 1'd0, cnfReqF_taggedReg[73:64], 1'd0, resp_respData__h6263 } ;
  assign MUX_cnfRespF_taggedReg$write_1__VAL_1 = { 1'd1, _x__h347 } ;
  assign MUX_currentReadRs_i$write_1__VAL_1 = currentReadRs_i + 16'd1 ;
  assign MUX_currentReadRs_i_1$write_1__VAL_1 = currentReadRs_i_1 + 16'd1 ;
  assign MUX_currentReadRs_i_2$write_1__VAL_1 = currentReadRs_i_2 + 16'd1 ;
  assign MUX_currentReadRs_i_3$write_1__VAL_1 = currentReadRs_i_3 + 16'd1 ;
  assign MUX_currentWriteRs_i$write_1__VAL_1 = currentWriteRs_i + 16'd1 ;
  assign MUX_currentWriteRs_i_1$write_1__VAL_1 = currentWriteRs_i_1 + 16'd1 ;
  assign MUX_currentWriteRs_i_2$write_1__VAL_1 = currentWriteRs_i_2 + 16'd1 ;
  assign MUX_currentWriteRs_i_3$write_1__VAL_1 = currentWriteRs_i_3 + 16'd1 ;
  assign MUX_destAddrRs_i$write_1__VAL_2 = destAddrRs_i + 32'd1 ;
  assign MUX_destAddrRs_i_1$write_1__VAL_2 = destAddrRs_i_1 + 32'd1 ;
  assign MUX_destAddrRs_i_2$write_1__VAL_2 = destAddrRs_i_2 + 32'd1 ;
  assign MUX_destAddrRs_i_3$write_1__VAL_2 = destAddrRs_i_3 + 32'd1 ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_1 =
             { 12'd2054, readAddrRs_i_3, 32'd0 } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_2 =
             { 12'd2052, readAddrRs_i_2, 32'd0 } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_3 =
             { 12'd2050, readAddrRs_i_1, 32'd0 } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_4 =
             { 12'd2048, readAddrRs_i, 32'd0 } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_5 =
             { 12'd1031, destAddrFs_i_3$first, responseDataFs_i_3$first } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_6 =
             { 12'd1029, destAddrFs_i_2$first, responseDataFs_i_2$first } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_7 =
             { 12'd1027, destAddrFs_i_1$first, responseDataFs_i_1$first } ;
  assign MUX_mmuReqF_rw_enq$wset_1__VAL_8 =
             { 12'd1025, destAddrFs_i$first, responseDataFs_i$first } ;
  assign MUX_readAddrRs_i$write_1__VAL_2 = readAddrRs_i + 32'd1 ;
  assign MUX_readAddrRs_i_3$write_1__VAL_2 = readAddrRs_i_3 + 32'd1 ;
  assign MUX_readAddrRs_i_1$write_1__VAL_2 = readAddrRs_i_1 + 32'd1 ;
  assign MUX_readAddrRs_i_2$write_1__VAL_2 = readAddrRs_i_2 + 32'd1 ;
  assign MUX_mmuRespF_taggedReg$write_1__VAL_1 =
             { 1'd1, mmuRespF_rw_enq$wget } ;

  // inlined wires
  assign cnfReqF_rw_enq$wget =
             { cfg_slave_req_putReq_reqOp,
               cfg_slave_req_putReq_reqInfo,
               cfg_slave_req_putReq_reqAddr,
               cfg_slave_req_putReq_reqData } ;
  assign cnfReqF_pw_deq$whas =
             WILL_FIRE_RL_writeConfig || WILL_FIRE_RL_readConfig ||
             WILL_FIRE_RL_unknownConfig ;
  assign cnfReqF_rw_enq$whas =
             cfg_slave_req_putReq_reqOp != 2'd0 &&
             (!cnfReqF_taggedReg[76] || cnfReqF_pw_deq$whas) ;
  assign cnfRespF_rw_enq$whas =
             WILL_FIRE_RL_readConfig || WILL_FIRE_RL_writeConfig ||
             WILL_FIRE_RL_unknownConfig ;
  assign mmuReqF_pw_deq$whas =
             EN_mmu_master_req_reqAccept && mmuReqF_taggedReg[76] ;
  always@(WILL_FIRE_RL_startRead_3 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_startRead_2 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_2 or
          WILL_FIRE_RL_startRead_1 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_3 or
          WILL_FIRE_RL_startRead or
          MUX_mmuReqF_rw_enq$wset_1__VAL_4 or
          WILL_FIRE_RL_startWrite_3 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_5 or
          WILL_FIRE_RL_startWrite_2 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_6 or
          WILL_FIRE_RL_startWrite_1 or
          MUX_mmuReqF_rw_enq$wset_1__VAL_7 or
          WILL_FIRE_RL_startWrite or MUX_mmuReqF_rw_enq$wset_1__VAL_8)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_startRead_3:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_startRead_2:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_2;
      WILL_FIRE_RL_startRead_1:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_3;
      WILL_FIRE_RL_startRead:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_4;
      WILL_FIRE_RL_startWrite_3:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_5;
      WILL_FIRE_RL_startWrite_2:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_6;
      WILL_FIRE_RL_startWrite_1:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_7;
      WILL_FIRE_RL_startWrite:
          mmuReqF_rw_enq$wget = MUX_mmuReqF_rw_enq$wset_1__VAL_8;
      default: mmuReqF_rw_enq$wget =
                   76'hAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign mmuReqF_rw_enq$whas =
             WILL_FIRE_RL_startRead_3 || WILL_FIRE_RL_startRead_2 ||
             WILL_FIRE_RL_startRead_1 ||
             WILL_FIRE_RL_startRead ||
             WILL_FIRE_RL_startWrite_3 ||
             WILL_FIRE_RL_startWrite_2 ||
             WILL_FIRE_RL_startWrite_1 ||
             WILL_FIRE_RL_startWrite ;
  assign mmuRespF_rw_enq$wget =
             { mmu_master_resp_putResp_respOp,
               mmu_master_resp_putResp_respInfo,
               mmu_master_resp_putResp_respAddr,
               mmu_master_resp_putResp_respData } ;
  assign mmuRespF_rw_enq$whas =
             mmu_master_resp_putResp_respOp && !mmuRespF_taggedReg[44] ;

  // register cnfReqF_taggedReg
  assign cnfReqF_taggedReg$D_IN =
             { cnfReqF_rw_enq$whas, cnfReqF_rw_enq$wget } ;
  assign cnfReqF_taggedReg$EN = CAN_FIRE_RL_cnfReqF_rule_update_final ;

  // register cnfRespF_taggedReg
  assign cnfRespF_taggedReg$D_IN =
             WILL_FIRE_RL_cnfRespF_rule_enq ?
               MUX_cnfRespF_taggedReg$write_1__VAL_1 :
               45'h0AAAAAAAAAAA ;
  assign cnfRespF_taggedReg$EN =
             WILL_FIRE_RL_cnfRespF_rule_enq ||
             WILL_FIRE_RL_cnfRespF_rule_deq ;

  // register currentReadRs_i
  assign currentReadRs_i$D_IN =
             WILL_FIRE_RL_startRead ?
               MUX_currentReadRs_i$write_1__VAL_1 :
               16'd0 ;
  assign currentReadRs_i$EN =
             WILL_FIRE_RL_startRead || WILL_FIRE_RL_markTransferDone ;

  // register currentReadRs_i_1
  assign currentReadRs_i_1$D_IN =
             WILL_FIRE_RL_startRead_1 ?
               MUX_currentReadRs_i_1$write_1__VAL_1 :
               16'd0 ;
  assign currentReadRs_i_1$EN =
             WILL_FIRE_RL_startRead_1 || WILL_FIRE_RL_markTransferDone_1 ;

  // register currentReadRs_i_2
  assign currentReadRs_i_2$D_IN =
             WILL_FIRE_RL_startRead_2 ?
               MUX_currentReadRs_i_2$write_1__VAL_1 :
               16'd0 ;
  assign currentReadRs_i_2$EN =
             WILL_FIRE_RL_startRead_2 || WILL_FIRE_RL_markTransferDone_2 ;

  // register currentReadRs_i_3
  assign currentReadRs_i_3$D_IN =
             WILL_FIRE_RL_startRead_3 ?
               MUX_currentReadRs_i_3$write_1__VAL_1 :
               16'd0 ;
  assign currentReadRs_i_3$EN =
             WILL_FIRE_RL_startRead_3 || WILL_FIRE_RL_markTransferDone_3 ;

  // register currentWriteRs_i
  assign currentWriteRs_i$D_IN =
             WILL_FIRE_RL_finishWrite ?
               MUX_currentWriteRs_i$write_1__VAL_1 :
               16'd0 ;
  assign currentWriteRs_i$EN =
             WILL_FIRE_RL_finishWrite || WILL_FIRE_RL_markTransferDone ;

  // register currentWriteRs_i_1
  assign currentWriteRs_i_1$D_IN =
             WILL_FIRE_RL_finishWrite_1 ?
               MUX_currentWriteRs_i_1$write_1__VAL_1 :
               16'd0 ;
  assign currentWriteRs_i_1$EN =
             WILL_FIRE_RL_finishWrite_1 || WILL_FIRE_RL_markTransferDone_1 ;

  // register currentWriteRs_i_2
  assign currentWriteRs_i_2$D_IN =
             WILL_FIRE_RL_finishWrite_2 ?
               MUX_currentWriteRs_i_2$write_1__VAL_1 :
               16'd0 ;
  assign currentWriteRs_i_2$EN =
             WILL_FIRE_RL_finishWrite_2 || WILL_FIRE_RL_markTransferDone_2 ;

  // register currentWriteRs_i_3
  assign currentWriteRs_i_3$D_IN =
             WILL_FIRE_RL_finishWrite_3 ?
               MUX_currentWriteRs_i_3$write_1__VAL_1 :
               16'd0 ;
  assign currentWriteRs_i_3$EN =
             WILL_FIRE_RL_finishWrite_3 || WILL_FIRE_RL_markTransferDone_3 ;

  // register destAddrRs_i
  assign destAddrRs_i$D_IN =
             MUX_destAddrRs_i$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_destAddrRs_i$write_1__VAL_2 ;
  assign destAddrRs_i$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd0 ||
             WILL_FIRE_RL_startRead ;

  // register destAddrRs_i_1
  assign destAddrRs_i_1$D_IN =
             MUX_destAddrRs_i_1$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_destAddrRs_i_1$write_1__VAL_2 ;
  assign destAddrRs_i_1$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd1 ||
             WILL_FIRE_RL_startRead_1 ;

  // register destAddrRs_i_2
  assign destAddrRs_i_2$D_IN =
             MUX_destAddrRs_i_2$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_destAddrRs_i_2$write_1__VAL_2 ;
  assign destAddrRs_i_2$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] == 4'd2 ||
             WILL_FIRE_RL_startRead_2 ;

  // register destAddrRs_i_3
  assign destAddrRs_i_3$D_IN =
             MUX_destAddrRs_i_3$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_destAddrRs_i_3$write_1__VAL_2 ;
  assign destAddrRs_i_3$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h08 &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ||
             WILL_FIRE_RL_startRead_3 ;

  // register dmaEnabledRs_i
  always@(MUX_dmaEnabledRs_i$write_1__SEL_1 or
          cnfReqF_taggedReg or EN_st_ch0_int or WILL_FIRE_RL_markTransferDone)
  case (1'b1)
    MUX_dmaEnabledRs_i$write_1__SEL_1:
        dmaEnabledRs_i$D_IN = cnfReqF_taggedReg[0];
    EN_st_ch0_int: dmaEnabledRs_i$D_IN = 1'd1;
    WILL_FIRE_RL_markTransferDone: dmaEnabledRs_i$D_IN = 1'd0;
    default: dmaEnabledRs_i$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign dmaEnabledRs_i$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd0 ||
             WILL_FIRE_RL_markTransferDone ||
             EN_st_ch0_int ;

  // register dmaEnabledRs_i_1
  always@(MUX_dmaEnabledRs_i_1$write_1__SEL_1 or
          cnfReqF_taggedReg or
          EN_st_ch1_int or WILL_FIRE_RL_markTransferDone_1)
  case (1'b1)
    MUX_dmaEnabledRs_i_1$write_1__SEL_1:
        dmaEnabledRs_i_1$D_IN = cnfReqF_taggedReg[0];
    EN_st_ch1_int: dmaEnabledRs_i_1$D_IN = 1'd1;
    WILL_FIRE_RL_markTransferDone_1: dmaEnabledRs_i_1$D_IN = 1'd0;
    default: dmaEnabledRs_i_1$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign dmaEnabledRs_i_1$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd1 ||
             WILL_FIRE_RL_markTransferDone_1 ||
             EN_st_ch1_int ;

  // register dmaEnabledRs_i_2
  always@(MUX_dmaEnabledRs_i_2$write_1__SEL_1 or
          cnfReqF_taggedReg or
          EN_st_ch2_int or WILL_FIRE_RL_markTransferDone_2)
  case (1'b1)
    MUX_dmaEnabledRs_i_2$write_1__SEL_1:
        dmaEnabledRs_i_2$D_IN = cnfReqF_taggedReg[0];
    EN_st_ch2_int: dmaEnabledRs_i_2$D_IN = 1'd1;
    WILL_FIRE_RL_markTransferDone_2: dmaEnabledRs_i_2$D_IN = 1'd0;
    default: dmaEnabledRs_i_2$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign dmaEnabledRs_i_2$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] == 4'd2 ||
             WILL_FIRE_RL_markTransferDone_2 ||
             EN_st_ch2_int ;

  // register dmaEnabledRs_i_3
  always@(MUX_dmaEnabledRs_i_3$write_1__SEL_1 or
          cnfReqF_taggedReg or
          EN_st_ch3_int or WILL_FIRE_RL_markTransferDone_3)
  case (1'b1)
    MUX_dmaEnabledRs_i_3$write_1__SEL_1:
        dmaEnabledRs_i_3$D_IN = cnfReqF_taggedReg[0];
    EN_st_ch3_int: dmaEnabledRs_i_3$D_IN = 1'd1;
    WILL_FIRE_RL_markTransferDone_3: dmaEnabledRs_i_3$D_IN = 1'd0;
    default: dmaEnabledRs_i_3$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign dmaEnabledRs_i_3$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0C &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ||
             WILL_FIRE_RL_markTransferDone_3 ||
             EN_st_ch3_int ;

  // register mmuReqF_taggedReg
  assign mmuReqF_taggedReg$D_IN =
             { mmuReqF_rw_enq$whas, mmuReqF_rw_enq$wget } ;
  assign mmuReqF_taggedReg$EN = CAN_FIRE_RL_mmuReqF_rule_update_final ;

  // register mmuRespF_taggedReg
  assign mmuRespF_taggedReg$D_IN =
             WILL_FIRE_RL_mmuRespF_rule_enq ?
               MUX_mmuRespF_taggedReg$write_1__VAL_1 :
               45'h0AAAAAAAAAAA ;
  assign mmuRespF_taggedReg$EN =
             WILL_FIRE_RL_mmuRespF_rule_enq ||
             WILL_FIRE_RL_mmuRespF_rule_deq ;

  // register readAddrRs_i
  assign readAddrRs_i$D_IN =
             MUX_readAddrRs_i$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_readAddrRs_i$write_1__VAL_2 ;
  assign readAddrRs_i$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd0 ||
             WILL_FIRE_RL_startRead ;

  // register readAddrRs_i_1
  assign readAddrRs_i_1$D_IN =
             MUX_readAddrRs_i_1$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_readAddrRs_i_1$write_1__VAL_2 ;
  assign readAddrRs_i_1$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd1 ||
             WILL_FIRE_RL_startRead_1 ;

  // register readAddrRs_i_2
  assign readAddrRs_i_2$D_IN =
             MUX_readAddrRs_i_2$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_readAddrRs_i_2$write_1__VAL_2 ;
  assign readAddrRs_i_2$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] == 4'd2 ||
             WILL_FIRE_RL_startRead_2 ;

  // register readAddrRs_i_3
  assign readAddrRs_i_3$D_IN =
             MUX_readAddrRs_i_3$write_1__SEL_1 ?
               cnfReqF_taggedReg[31:0] :
               MUX_readAddrRs_i_3$write_1__VAL_2 ;
  assign readAddrRs_i_3$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h0 &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ||
             WILL_FIRE_RL_startRead_3 ;

  // register readCntrRs_i
  assign readCntrRs_i$D_IN = cnfReqF_taggedReg[15:0] ;
  assign readCntrRs_i$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h04 &&
             cnfReqF_taggedReg[43:40] == 4'd0 ;

  // register readCntrRs_i_1
  assign readCntrRs_i_1$D_IN = cnfReqF_taggedReg[15:0] ;
  assign readCntrRs_i_1$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h04 &&
             cnfReqF_taggedReg[43:40] == 4'd1 ;

  // register readCntrRs_i_2
  assign readCntrRs_i_2$D_IN = cnfReqF_taggedReg[15:0] ;
  assign readCntrRs_i_2$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h04 &&
             cnfReqF_taggedReg[43:40] == 4'd2 ;

  // register readCntrRs_i_3
  assign readCntrRs_i_3$D_IN = cnfReqF_taggedReg[15:0] ;
  assign readCntrRs_i_3$EN =
             WILL_FIRE_RL_writeConfig && cnfReqF_taggedReg[39:32] == 8'h04 &&
             cnfReqF_taggedReg[43:40] != 4'd0 &&
             cnfReqF_taggedReg[43:40] != 4'd1 &&
             cnfReqF_taggedReg[43:40] != 4'd2 ;

  // submodule destAddrFs_i
  assign destAddrFs_i$enq_x1 = destAddrRs_i ;
  assign destAddrFs_i$EN_deq = CAN_FIRE_RL_startWrite ;
  assign destAddrFs_i$EN_enq = WILL_FIRE_RL_startRead ;
  assign destAddrFs_i$EN_clear = 1'b0 ;

  // submodule destAddrFs_i_1
  assign destAddrFs_i_1$enq_x1 = destAddrRs_i_1 ;
  assign destAddrFs_i_1$EN_deq = WILL_FIRE_RL_startWrite_1 ;
  assign destAddrFs_i_1$EN_enq = WILL_FIRE_RL_startRead_1 ;
  assign destAddrFs_i_1$EN_clear = 1'b0 ;

  // submodule destAddrFs_i_2
  assign destAddrFs_i_2$enq_x1 = destAddrRs_i_2 ;
  assign destAddrFs_i_2$EN_deq = WILL_FIRE_RL_startWrite_2 ;
  assign destAddrFs_i_2$EN_enq = WILL_FIRE_RL_startRead_2 ;
  assign destAddrFs_i_2$EN_clear = 1'b0 ;

  // submodule destAddrFs_i_3
  assign destAddrFs_i_3$enq_x1 = destAddrRs_i_3 ;
  assign destAddrFs_i_3$EN_deq = WILL_FIRE_RL_startWrite_3 ;
  assign destAddrFs_i_3$EN_enq = WILL_FIRE_RL_startRead_3 ;
  assign destAddrFs_i_3$EN_clear = 1'b0 ;

  // submodule responseDataFs_i
  assign responseDataFs_i$EN_deq = CAN_FIRE_RL_startWrite ;
  assign responseDataFs_i$enq_x1 =
             mmuRespF_rw_enq$whas ?
               mmuRespF_rw_enq$wget[31:0] :
               mmuRespF_taggedReg[31:0] ;
  assign responseDataFs_i$EN_enq = WILL_FIRE_RL_finishRead ;
  assign responseDataFs_i$EN_clear = 1'b0 ;

  // submodule responseDataFs_i_1
  assign responseDataFs_i_1$EN_clear = 1'b0 ;
  assign responseDataFs_i_1$EN_deq = WILL_FIRE_RL_startWrite_1 ;
  assign responseDataFs_i_1$enq_x1 = responseDataFs_i$enq_x1 ;
  assign responseDataFs_i_1$EN_enq = WILL_FIRE_RL_finishRead_1 ;

  // submodule responseDataFs_i_2
  assign responseDataFs_i_2$EN_deq = WILL_FIRE_RL_startWrite_2 ;
  assign responseDataFs_i_2$enq_x1 = responseDataFs_i$enq_x1 ;
  assign responseDataFs_i_2$EN_enq = WILL_FIRE_RL_finishRead_2 ;
  assign responseDataFs_i_2$EN_clear = 1'b0 ;

  // submodule responseDataFs_i_3
  assign responseDataFs_i_3$EN_deq = WILL_FIRE_RL_startWrite_3 ;
  assign responseDataFs_i_3$enq_x1 = responseDataFs_i$enq_x1 ;
  assign responseDataFs_i_3$EN_enq = WILL_FIRE_RL_finishRead_3 ;
  assign responseDataFs_i_3$EN_clear = 1'b0 ;

  // remaining internal signals
  assign IF_mmuRespF_rw_enq_whas__04_THEN_mmuRespF_rw_e_ETC___d301 =
             mmuRespF_rw_enq$whas ?
               mmuRespF_rw_enq$wget[42:33] :
               mmuRespF_taggedReg[42:33] ;
  always@(cnfReqF_taggedReg or
          readCntrRs_i_3 or readCntrRs_i or readCntrRs_i_1 or readCntrRs_i_2)
  begin
    case (cnfReqF_taggedReg[43:40])
      4'd0: x__h6559 = readCntrRs_i;
      4'd1: x__h6559 = readCntrRs_i_1;
      4'd2: x__h6559 = readCntrRs_i_2;
      default: x__h6559 = readCntrRs_i_3;
    endcase
  end
  always@(cnfReqF_taggedReg or
          dmaEnabledRs_i_3 or
          dmaEnabledRs_i or dmaEnabledRs_i_1 or dmaEnabledRs_i_2)
  begin
    case (cnfReqF_taggedReg[43:40])
      4'd0: x__h6411 = dmaEnabledRs_i;
      4'd1: x__h6411 = dmaEnabledRs_i_1;
      4'd2: x__h6411 = dmaEnabledRs_i_2;
      default: x__h6411 = dmaEnabledRs_i_3;
    endcase
  end
  always@(cnfReqF_taggedReg or
          readAddrRs_i_3 or readAddrRs_i or readAddrRs_i_1 or readAddrRs_i_2)
  begin
    case (cnfReqF_taggedReg[43:40])
      4'd0:
          CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1 =
              readAddrRs_i;
      4'd1:
          CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1 =
              readAddrRs_i_1;
      4'd2:
          CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1 =
              readAddrRs_i_2;
      default: CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1 =
                   readAddrRs_i_3;
    endcase
  end
  always@(cnfReqF_taggedReg or
          destAddrRs_i or destAddrRs_i_1 or destAddrRs_i_2 or destAddrRs_i_3)
  case (1'b1)
    cnfReqF_taggedReg[43:40] == 4'd0:
        PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2 = destAddrRs_i;
    cnfReqF_taggedReg[43:40] == 4'd1:
        PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2 =
            destAddrRs_i_1;
    cnfReqF_taggedReg[43:40] == 4'd2:
        PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2 =
            destAddrRs_i_2;
    default: PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2 =
                 destAddrRs_i_3;
  endcase
  always@(cnfReqF_taggedReg or
          CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1 or
          x__h6559 or
          PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2 or x__h6411)
  begin
    case (cnfReqF_taggedReg[39:32])
      8'h0:
          resp_respData__h6263 =
              CASE_cnfReqF_taggedReg_BITS_43_TO_40_readAddrR_ETC__q1;
      8'h04: resp_respData__h6263 = { 16'd0, x__h6559 };
      8'h08:
          resp_respData__h6263 =
              PRIMUX_cnfReqF_taggedReg_BITS_43_TO_40_EQ_0_de_ETC__q2;
      8'h0C: resp_respData__h6263 = { 31'd0, x__h6411 };
      default: resp_respData__h6263 = 32'd0;
    endcase
  end
  always@(WILL_FIRE_RL_readConfig or
          MUX_cnfRespF_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_writeConfig or
          MUX_cnfRespF_rw_enq$wset_1__VAL_2 or
          WILL_FIRE_RL_unknownConfig or MUX_cnfRespF_rw_enq$wset_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_readConfig: _x__h347 = MUX_cnfRespF_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_writeConfig: _x__h347 = MUX_cnfRespF_rw_enq$wset_1__VAL_2;
      WILL_FIRE_RL_unknownConfig:
          _x__h347 = MUX_cnfRespF_rw_enq$wset_1__VAL_3;
      default: _x__h347 = 44'hAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        cnfReqF_taggedReg <= `BSV_ASSIGNMENT_DELAY 77'h0AAAAAAAAAAAAAAAAAAA;
        cnfRespF_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        currentReadRs_i <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentReadRs_i_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentReadRs_i_2 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentReadRs_i_3 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentWriteRs_i <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentWriteRs_i_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentWriteRs_i_2 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        currentWriteRs_i_3 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        destAddrRs_i <= `BSV_ASSIGNMENT_DELAY 32'd0;
        destAddrRs_i_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        destAddrRs_i_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        destAddrRs_i_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        dmaEnabledRs_i <= `BSV_ASSIGNMENT_DELAY 1'd0;
        dmaEnabledRs_i_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
        dmaEnabledRs_i_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
        dmaEnabledRs_i_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
        mmuReqF_taggedReg <= `BSV_ASSIGNMENT_DELAY 77'h0AAAAAAAAAAAAAAAAAAA;
        mmuRespF_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        readAddrRs_i <= `BSV_ASSIGNMENT_DELAY 32'd0;
        readAddrRs_i_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        readAddrRs_i_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        readAddrRs_i_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
        readCntrRs_i <= `BSV_ASSIGNMENT_DELAY 16'd0;
        readCntrRs_i_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        readCntrRs_i_2 <= `BSV_ASSIGNMENT_DELAY 16'd0;
        readCntrRs_i_3 <= `BSV_ASSIGNMENT_DELAY 16'd0;
      end
    else
      begin
        if (cnfReqF_taggedReg$EN)
          cnfReqF_taggedReg <= `BSV_ASSIGNMENT_DELAY cnfReqF_taggedReg$D_IN;
        if (cnfRespF_taggedReg$EN)
          cnfRespF_taggedReg <= `BSV_ASSIGNMENT_DELAY cnfRespF_taggedReg$D_IN;
        if (currentReadRs_i$EN)
          currentReadRs_i <= `BSV_ASSIGNMENT_DELAY currentReadRs_i$D_IN;
        if (currentReadRs_i_1$EN)
          currentReadRs_i_1 <= `BSV_ASSIGNMENT_DELAY currentReadRs_i_1$D_IN;
        if (currentReadRs_i_2$EN)
          currentReadRs_i_2 <= `BSV_ASSIGNMENT_DELAY currentReadRs_i_2$D_IN;
        if (currentReadRs_i_3$EN)
          currentReadRs_i_3 <= `BSV_ASSIGNMENT_DELAY currentReadRs_i_3$D_IN;
        if (currentWriteRs_i$EN)
          currentWriteRs_i <= `BSV_ASSIGNMENT_DELAY currentWriteRs_i$D_IN;
        if (currentWriteRs_i_1$EN)
          currentWriteRs_i_1 <= `BSV_ASSIGNMENT_DELAY currentWriteRs_i_1$D_IN;
        if (currentWriteRs_i_2$EN)
          currentWriteRs_i_2 <= `BSV_ASSIGNMENT_DELAY currentWriteRs_i_2$D_IN;
        if (currentWriteRs_i_3$EN)
          currentWriteRs_i_3 <= `BSV_ASSIGNMENT_DELAY currentWriteRs_i_3$D_IN;
        if (destAddrRs_i$EN)
          destAddrRs_i <= `BSV_ASSIGNMENT_DELAY destAddrRs_i$D_IN;
        if (destAddrRs_i_1$EN)
          destAddrRs_i_1 <= `BSV_ASSIGNMENT_DELAY destAddrRs_i_1$D_IN;
        if (destAddrRs_i_2$EN)
          destAddrRs_i_2 <= `BSV_ASSIGNMENT_DELAY destAddrRs_i_2$D_IN;
        if (destAddrRs_i_3$EN)
          destAddrRs_i_3 <= `BSV_ASSIGNMENT_DELAY destAddrRs_i_3$D_IN;
        if (dmaEnabledRs_i$EN)
          dmaEnabledRs_i <= `BSV_ASSIGNMENT_DELAY dmaEnabledRs_i$D_IN;
        if (dmaEnabledRs_i_1$EN)
          dmaEnabledRs_i_1 <= `BSV_ASSIGNMENT_DELAY dmaEnabledRs_i_1$D_IN;
        if (dmaEnabledRs_i_2$EN)
          dmaEnabledRs_i_2 <= `BSV_ASSIGNMENT_DELAY dmaEnabledRs_i_2$D_IN;
        if (dmaEnabledRs_i_3$EN)
          dmaEnabledRs_i_3 <= `BSV_ASSIGNMENT_DELAY dmaEnabledRs_i_3$D_IN;
        if (mmuReqF_taggedReg$EN)
          mmuReqF_taggedReg <= `BSV_ASSIGNMENT_DELAY mmuReqF_taggedReg$D_IN;
        if (mmuRespF_taggedReg$EN)
          mmuRespF_taggedReg <= `BSV_ASSIGNMENT_DELAY mmuRespF_taggedReg$D_IN;
        if (readAddrRs_i$EN)
          readAddrRs_i <= `BSV_ASSIGNMENT_DELAY readAddrRs_i$D_IN;
        if (readAddrRs_i_1$EN)
          readAddrRs_i_1 <= `BSV_ASSIGNMENT_DELAY readAddrRs_i_1$D_IN;
        if (readAddrRs_i_2$EN)
          readAddrRs_i_2 <= `BSV_ASSIGNMENT_DELAY readAddrRs_i_2$D_IN;
        if (readAddrRs_i_3$EN)
          readAddrRs_i_3 <= `BSV_ASSIGNMENT_DELAY readAddrRs_i_3$D_IN;
        if (readCntrRs_i$EN)
          readCntrRs_i <= `BSV_ASSIGNMENT_DELAY readCntrRs_i$D_IN;
        if (readCntrRs_i_1$EN)
          readCntrRs_i_1 <= `BSV_ASSIGNMENT_DELAY readCntrRs_i_1$D_IN;
        if (readCntrRs_i_2$EN)
          readCntrRs_i_2 <= `BSV_ASSIGNMENT_DELAY readCntrRs_i_2$D_IN;
        if (readCntrRs_i_3$EN)
          readCntrRs_i_3 <= `BSV_ASSIGNMENT_DELAY readCntrRs_i_3$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cnfReqF_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    cnfRespF_taggedReg = 45'h0AAAAAAAAAAA;
    currentReadRs_i = 16'hAAAA;
    currentReadRs_i_1 = 16'hAAAA;
    currentReadRs_i_2 = 16'hAAAA;
    currentReadRs_i_3 = 16'hAAAA;
    currentWriteRs_i = 16'hAAAA;
    currentWriteRs_i_1 = 16'hAAAA;
    currentWriteRs_i_2 = 16'hAAAA;
    currentWriteRs_i_3 = 16'hAAAA;
    destAddrRs_i = 32'hAAAAAAAA;
    destAddrRs_i_1 = 32'hAAAAAAAA;
    destAddrRs_i_2 = 32'hAAAAAAAA;
    destAddrRs_i_3 = 32'hAAAAAAAA;
    dmaEnabledRs_i = 1'h0;
    dmaEnabledRs_i_1 = 1'h0;
    dmaEnabledRs_i_2 = 1'h0;
    dmaEnabledRs_i_3 = 1'h0;
    mmuReqF_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    mmuRespF_taggedReg = 45'h0AAAAAAAAAAA;
    readAddrRs_i = 32'hAAAAAAAA;
    readAddrRs_i_1 = 32'hAAAAAAAA;
    readAddrRs_i_2 = 32'hAAAAAAAA;
    readAddrRs_i_3 = 32'hAAAAAAAA;
    readCntrRs_i = 16'hAAAA;
    readCntrRs_i_1 = 16'hAAAA;
    readCntrRs_i_2 = 16'hAAAA;
    readCntrRs_i_3 = 16'hAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkDMA

        