//
// Generated by Bluespec Compiler, version 2006.11 (build 9629, 2006-11-11)
// 
// On Mon Feb 12 14:06:18 EST 2007
// 
// Method conflict info:
// Method: initiator_0_slave_req_putReq
// Conflict-free: initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: initiator_0_slave_req_putReq
//  
// Method: initiator_0_slave_req_reqAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: initiator_0_slave_resp_getResp
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: initiator_0_slave_resp_respAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: initiator_0_slave_resp_respAccept
//  
// Method: initiator_1_slave_req_putReq
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: initiator_1_slave_req_putReq
//  
// Method: initiator_1_slave_req_reqAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: initiator_1_slave_resp_getResp
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: initiator_1_slave_resp_respAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: initiator_1_slave_resp_respAccept
//  
// Method: target_0_master_req_getReq
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: target_0_master_req_reqAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: target_0_master_req_reqAccept
//  
// Method: target_0_master_resp_putResp
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: target_0_master_resp_putResp
//  
// Method: target_0_master_resp_respAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: target_1_master_req_getReq
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// Method: target_1_master_req_reqAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
// Conflicts: target_1_master_req_reqAccept
//  
// Method: target_1_master_resp_putResp
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_respAccept
// Conflicts: target_1_master_resp_putResp
//  
// Method: target_1_master_resp_respAccept
// Conflict-free: initiator_0_slave_req_putReq,
//                initiator_0_slave_req_reqAccept,
//                initiator_0_slave_resp_getResp,
//                initiator_0_slave_resp_respAccept,
//                initiator_1_slave_req_putReq,
//                initiator_1_slave_req_reqAccept,
//                initiator_1_slave_resp_getResp,
//                initiator_1_slave_resp_respAccept,
//                target_0_master_req_getReq,
//                target_0_master_req_reqAccept,
//                target_0_master_resp_putResp,
//                target_0_master_resp_respAccept,
//                target_1_master_req_getReq,
//                target_1_master_req_reqAccept,
//                target_1_master_resp_putResp,
//                target_1_master_resp_respAccept
//  
// 
// Ports:
// Name                         I/O  size props
// initiator_0_slave_req_reqAccept O     1
// initiator_0_slave_resp_getResp O    44
// initiator_1_slave_req_reqAccept O     1
// initiator_1_slave_resp_getResp O    44
// target_0_master_req_getReq     O    76
// target_0_master_resp_respAccept O     1
// target_1_master_req_getReq     O    76
// target_1_master_resp_respAccept O     1
// CLK                            I     1
// RST_N                          I     1
// initiator_0_slave_req_putReq_req I    76
// initiator_0_slave_resp_respAccept_accept I     1
// initiator_1_slave_req_putReq_req I    76
// initiator_1_slave_resp_respAccept_accept I     1
// target_0_master_req_reqAccept_accept I     1
// target_0_master_resp_putResp_resp I    44
// target_1_master_req_reqAccept_accept I     1
// target_1_master_resp_putResp_resp I    44
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkSwitch(CLK,
                RST_N,
                
                initiator_0_slave_req_putReq_req,
                
                initiator_0_slave_req_reqAccept,
                
                initiator_0_slave_resp_getResp,
                
                initiator_0_slave_resp_respAccept_accept,
                
                initiator_1_slave_req_putReq_req,
                
                initiator_1_slave_req_reqAccept,
                
                initiator_1_slave_resp_getResp,
                
                initiator_1_slave_resp_respAccept_accept,
                
                target_0_master_req_getReq,
                
                target_0_master_req_reqAccept_accept,
                
                target_0_master_resp_putResp_resp,
                
                target_0_master_resp_respAccept,
                
                target_1_master_req_getReq,
                
                target_1_master_req_reqAccept_accept,
                
                target_1_master_resp_putResp_resp,
                
                target_1_master_resp_respAccept);
  input  CLK;
  input  RST_N;
  
  // action method initiator_0_slave_req_putReq
  input  [75 : 0] initiator_0_slave_req_putReq_req;
  
  // value method initiator_0_slave_req_reqAccept
  output initiator_0_slave_req_reqAccept;
  
  // value method initiator_0_slave_resp_getResp
  output [43 : 0] initiator_0_slave_resp_getResp;
  
  // action method initiator_0_slave_resp_respAccept
  input  initiator_0_slave_resp_respAccept_accept;
  
  // action method initiator_1_slave_req_putReq
  input  [75 : 0] initiator_1_slave_req_putReq_req;
  
  // value method initiator_1_slave_req_reqAccept
  output initiator_1_slave_req_reqAccept;
  
  // value method initiator_1_slave_resp_getResp
  output [43 : 0] initiator_1_slave_resp_getResp;
  
  // action method initiator_1_slave_resp_respAccept
  input  initiator_1_slave_resp_respAccept_accept;
  
  // value method target_0_master_req_getReq
  output [75 : 0] target_0_master_req_getReq;
  
  // action method target_0_master_req_reqAccept
  input  target_0_master_req_reqAccept_accept;
  
  // action method target_0_master_resp_putResp
  input  [43 : 0] target_0_master_resp_putResp_resp;
  
  // value method target_0_master_resp_respAccept
  output target_0_master_resp_respAccept;
  
  // value method target_1_master_req_getReq
  output [75 : 0] target_1_master_req_getReq;
  
  // action method target_1_master_req_reqAccept
  input  target_1_master_req_reqAccept_accept;
  
  // action method target_1_master_resp_putResp
  input  [43 : 0] target_1_master_resp_putResp_resp;
  
  // value method target_1_master_resp_respAccept
  output target_1_master_resp_respAccept;

  // signals for module outputs
  wire [75 : 0] target_0_master_req_getReq, target_1_master_req_getReq;
  wire [43 : 0] initiator_0_slave_resp_getResp,
                initiator_1_slave_resp_getResp;
  wire initiator_0_slave_req_reqAccept,
       initiator_1_slave_req_reqAccept,
       target_0_master_resp_respAccept,
       target_1_master_resp_respAccept;

  // inlined wires
  reg [75 : 0] to_target_0_rw_enq$wget;
  reg [43 : 0] to_initiator_0_rw_enq$wget, to_initiator_1_rw_enq$wget;
  wire from_initiator_0_pw_deq$whas,
       from_initiator_0_rw_enq$whas,
       from_initiator_1_pw_deq$whas,
       from_initiator_1_rw_enq$whas,
       from_target_0_rw_enq$whas,
       from_target_1_rw_enq$whas,
       to_initiator_0_pw_deq$whas,
       to_initiator_0_rw_enq$whas,
       to_initiator_1_pw_deq$whas,
       to_initiator_1_rw_enq$whas,
       to_target_0_rw_enq$whas,
       to_target_1_rw_enq$whas;

  // register from_initiator_0_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] from_initiator_0_taggedReg;
  wire [76 : 0] from_initiator_0_taggedReg$D_IN;
  wire from_initiator_0_taggedReg$EN;

  // register from_initiator_1_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] from_initiator_1_taggedReg;
  wire [76 : 0] from_initiator_1_taggedReg$D_IN;
  wire from_initiator_1_taggedReg$EN;

  // register from_target_0_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] from_target_0_taggedReg;
  wire [44 : 0] from_target_0_taggedReg$D_IN;
  wire from_target_0_taggedReg$EN;

  // register from_target_1_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] from_target_1_taggedReg;
  wire [44 : 0] from_target_1_taggedReg$D_IN;
  wire from_target_1_taggedReg$EN;

  // register to_initiator_0_round_robin
  //  When this register is TRUE, responses from 
  //  target 0 will go to initiator 0 
  reg to_initiator_0_round_robin;
  wire to_initiator_0_round_robin$D_IN, to_initiator_0_round_robin$EN;

  // register to_initiator_0_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] to_initiator_0_taggedReg;
  wire [44 : 0] to_initiator_0_taggedReg$D_IN;
  wire to_initiator_0_taggedReg$EN;

  // register to_initiator_1_round_robin
  //  When this register is TRUE, responses from 
  //  target 0 will go to initiator 1 
  reg to_initiator_1_round_robin;
  wire to_initiator_1_round_robin$D_IN, to_initiator_1_round_robin$EN;

  // register to_initiator_1_taggedReg
  // this register holds the data in the pipelineFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [44 : 0] to_initiator_1_taggedReg;
  wire [44 : 0] to_initiator_1_taggedReg$D_IN;
  wire to_initiator_1_taggedReg$EN;

  // register to_target_0_round_robin
  //  When this register is TRUE, requsts from 
  //  initiator 0 will go to target 0 
  reg to_target_0_round_robin;
  wire to_target_0_round_robin$D_IN, to_target_0_round_robin$EN;

  // register to_target_0_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] to_target_0_taggedReg;
  wire [76 : 0] to_target_0_taggedReg$D_IN;
  wire to_target_0_taggedReg$EN;

  // register to_target_1_round_robin
  //  When this register is TRUE, requsts from 
  //  initiator 0 will go to target 1 
  reg to_target_1_round_robin;
  wire to_target_1_round_robin$D_IN, to_target_1_round_robin$EN;

  // register to_target_1_taggedReg
  // this register holds the data in the bypassFifo,
  // as well as an extra bit to note whether the data is valid or not
  reg [76 : 0] to_target_1_taggedReg;
  wire [76 : 0] to_target_1_taggedReg$D_IN;
  wire to_target_1_taggedReg$EN;

  // rule scheduling signals
  wire CAN_FIRE_RL_both_initiators_to_target_0,
       CAN_FIRE_RL_both_initiators_to_target_1,
       CAN_FIRE_RL_both_targets_to_initiator_0,
       CAN_FIRE_RL_both_targets_to_initiator_1,
       CAN_FIRE_RL_from_initiator_0_rule_update_final,
       CAN_FIRE_RL_from_initiator_1_rule_update_final,
       CAN_FIRE_RL_from_target_0_rule_deq,
       CAN_FIRE_RL_from_target_0_rule_enq,
       CAN_FIRE_RL_from_target_1_rule_deq,
       CAN_FIRE_RL_from_target_1_rule_enq,
       CAN_FIRE_RL_initiator_0_to_target_0,
       CAN_FIRE_RL_initiator_0_to_target_1,
       CAN_FIRE_RL_initiator_1_to_target_0,
       CAN_FIRE_RL_initiator_1_to_target_1,
       CAN_FIRE_RL_target_0_to_initiator_0,
       CAN_FIRE_RL_target_0_to_initiator_1,
       CAN_FIRE_RL_target_1_to_initiator_0,
       CAN_FIRE_RL_target_1_to_initiator_1,
       CAN_FIRE_RL_to_initiator_0_rule_update_final,
       CAN_FIRE_RL_to_initiator_1_rule_update_final,
       CAN_FIRE_RL_to_target_0_rule_deq,
       CAN_FIRE_RL_to_target_0_rule_enq,
       CAN_FIRE_RL_to_target_1_rule_deq,
       CAN_FIRE_RL_to_target_1_rule_enq,
       CAN_FIRE_initiator_0_slave_req_putReq,
       CAN_FIRE_initiator_0_slave_resp_respAccept,
       CAN_FIRE_initiator_1_slave_req_putReq,
       CAN_FIRE_initiator_1_slave_resp_respAccept,
       CAN_FIRE_target_0_master_req_reqAccept,
       CAN_FIRE_target_0_master_resp_putResp,
       CAN_FIRE_target_1_master_req_reqAccept,
       CAN_FIRE_target_1_master_resp_putResp,
       WILL_FIRE_RL_both_initiators_to_target_0,
       WILL_FIRE_RL_both_initiators_to_target_1,
       WILL_FIRE_RL_both_targets_to_initiator_0,
       WILL_FIRE_RL_both_targets_to_initiator_1,
       WILL_FIRE_RL_from_initiator_0_rule_update_final,
       WILL_FIRE_RL_from_initiator_1_rule_update_final,
       WILL_FIRE_RL_from_target_0_rule_deq,
       WILL_FIRE_RL_from_target_0_rule_enq,
       WILL_FIRE_RL_from_target_1_rule_deq,
       WILL_FIRE_RL_from_target_1_rule_enq,
       WILL_FIRE_RL_initiator_0_to_target_0,
       WILL_FIRE_RL_initiator_0_to_target_1,
       WILL_FIRE_RL_initiator_1_to_target_0,
       WILL_FIRE_RL_initiator_1_to_target_1,
       WILL_FIRE_RL_target_0_to_initiator_0,
       WILL_FIRE_RL_target_0_to_initiator_1,
       WILL_FIRE_RL_target_1_to_initiator_0,
       WILL_FIRE_RL_target_1_to_initiator_1,
       WILL_FIRE_RL_to_initiator_0_rule_update_final,
       WILL_FIRE_RL_to_initiator_1_rule_update_final,
       WILL_FIRE_RL_to_target_0_rule_deq,
       WILL_FIRE_RL_to_target_0_rule_enq,
       WILL_FIRE_RL_to_target_1_rule_deq,
       WILL_FIRE_RL_to_target_1_rule_enq,
       WILL_FIRE_initiator_0_slave_req_putReq,
       WILL_FIRE_initiator_0_slave_resp_respAccept,
       WILL_FIRE_initiator_1_slave_req_putReq,
       WILL_FIRE_initiator_1_slave_resp_respAccept,
       WILL_FIRE_target_0_master_req_reqAccept,
       WILL_FIRE_target_0_master_resp_putResp,
       WILL_FIRE_target_1_master_req_reqAccept,
       WILL_FIRE_target_1_master_resp_putResp;

  // inputs to muxes for submodule ports
  wire [76 : 0] MUX_to_target_0_taggedReg$write_1__VAL_1,
                MUX_to_target_1_taggedReg$write_1__VAL_1;
  wire [75 : 0] MUX_to_target_0_rw_enq$wset_1__VAL_1,
                MUX_to_target_1_rw_enq$wset_1__VAL_1;
  wire [44 : 0] MUX_from_target_0_taggedReg$write_1__VAL_1,
                MUX_from_target_1_taggedReg$write_1__VAL_1;
  wire [43 : 0] MUX_to_initiator_0_rw_enq$wset_1__VAL_1,
                MUX_to_initiator_1_rw_enq$wset_1__VAL_1;

  // remaining internal signals
  reg [75 : 0] _x__h1018;
  reg [1 : 0] IF_to_target_0_taggedReg_07_BIT_76_08_OR_to_ta_ETC___d265,
              IF_to_target_1_taggedReg_7_BIT_76_8_OR_to_targ_ETC___d263;
  wire [43 : 0] IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235,
                IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237;
  wire [42 : 0] IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d280,
                IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d279;
  wire [32 : 0] IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d285,
                IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d286;
  wire [31 : 0] target_0_master_req_getReq_reqAddr__h2786,
                target_0_master_req_getReq_reqData__h2787,
                target_1_master_req_getReq_reqAddr__h2890,
                target_1_master_req_getReq_reqData__h2891;
  wire [9 : 0] target_0_master_req_getReq_reqInfo__h2785,
               target_1_master_req_getReq_reqInfo__h2889;
  wire IF_from_target_0_rw_enq_whas__0_THEN_NOT_from__ETC___d244,
       IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236,
       IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d245,
       IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d234,
       NOT_to_initiator_1_taggedReg_BIT_44_OR_to_init_ETC___d58,
       from_target_0_taggedReg_8_BIT_44_9_OR_from_tar_ETC___d80,
       x_initiator_0_slave_req_reqAccept__h2557,
       x_target_0_master_resp_respAccept__h2567,
       x_target_1_master_resp_respAccept__h2571;

  // action method initiator_0_slave_req_putReq
  assign WILL_FIRE_initiator_0_slave_req_putReq = 1'b1 ;
  assign CAN_FIRE_initiator_0_slave_req_putReq = 1'b1 ;

  // value method initiator_0_slave_req_reqAccept
  assign initiator_0_slave_req_reqAccept =
             !from_initiator_0_taggedReg[76] || from_initiator_0_pw_deq$whas ;

  // value method initiator_0_slave_resp_getResp
  assign initiator_0_slave_resp_getResp =
             { to_initiator_0_taggedReg[44] && to_initiator_0_taggedReg[43],
               to_initiator_0_taggedReg[42:0] } ;

  // action method initiator_0_slave_resp_respAccept
  assign WILL_FIRE_initiator_0_slave_resp_respAccept = 1'b1 ;
  assign CAN_FIRE_initiator_0_slave_resp_respAccept = 1'b1 ;

  // action method initiator_1_slave_req_putReq
  assign WILL_FIRE_initiator_1_slave_req_putReq = 1'b1 ;
  assign CAN_FIRE_initiator_1_slave_req_putReq = 1'b1 ;

  // value method initiator_1_slave_req_reqAccept
  assign initiator_1_slave_req_reqAccept =
             !from_initiator_1_taggedReg[76] || from_initiator_1_pw_deq$whas ;

  // value method initiator_1_slave_resp_getResp
  assign initiator_1_slave_resp_getResp =
             { to_initiator_1_taggedReg[44] && to_initiator_1_taggedReg[43],
               to_initiator_1_taggedReg[42:0] } ;

  // action method initiator_1_slave_resp_respAccept
  assign WILL_FIRE_initiator_1_slave_resp_respAccept = 1'b1 ;
  assign CAN_FIRE_initiator_1_slave_resp_respAccept = 1'b1 ;

  // value method target_0_master_req_getReq
  assign target_0_master_req_getReq =
             { IF_to_target_0_taggedReg_07_BIT_76_08_OR_to_ta_ETC___d265,
               target_0_master_req_getReq_reqInfo__h2785,
               target_0_master_req_getReq_reqAddr__h2786,
               target_0_master_req_getReq_reqData__h2787 } ;

  // action method target_0_master_req_reqAccept
  assign WILL_FIRE_target_0_master_req_reqAccept = 1'b1 ;
  assign CAN_FIRE_target_0_master_req_reqAccept = 1'b1 ;

  // action method target_0_master_resp_putResp
  assign WILL_FIRE_target_0_master_resp_putResp = 1'b1 ;
  assign CAN_FIRE_target_0_master_resp_putResp = 1'b1 ;

  // value method target_0_master_resp_respAccept
  assign target_0_master_resp_respAccept = !from_target_0_taggedReg[44] ;

  // value method target_1_master_req_getReq
  assign target_1_master_req_getReq =
             { IF_to_target_1_taggedReg_7_BIT_76_8_OR_to_targ_ETC___d263,
               target_1_master_req_getReq_reqInfo__h2889,
               target_1_master_req_getReq_reqAddr__h2890,
               target_1_master_req_getReq_reqData__h2891 } ;

  // action method target_1_master_req_reqAccept
  assign WILL_FIRE_target_1_master_req_reqAccept = 1'b1 ;
  assign CAN_FIRE_target_1_master_req_reqAccept = 1'b1 ;

  // action method target_1_master_resp_putResp
  assign WILL_FIRE_target_1_master_resp_putResp = 1'b1 ;
  assign CAN_FIRE_target_1_master_resp_putResp = 1'b1 ;

  // value method target_1_master_resp_respAccept
  assign target_1_master_resp_respAccept = !from_target_1_taggedReg[44] ;

  // rule RL_both_initiators_to_target_0
  //   This rule will fire whenever both initiators are
  //   trying to send a request to target 0
  assign WILL_FIRE_RL_both_initiators_to_target_0 =
             from_initiator_0_taggedReg[76] &&
             !to_target_0_taggedReg[76] &&
             (from_initiator_0_taggedReg[32] ||
              from_initiator_1_taggedReg[76]) &&
             (to_target_0_round_robin || from_initiator_1_taggedReg[76]) &&
             !from_initiator_0_taggedReg[32] &&
             !from_initiator_1_taggedReg[32] ;
  assign CAN_FIRE_RL_both_initiators_to_target_0 =
             WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_initiator_0_to_target_0
  //   This rule will fire whenever initiator 0 is
  //   trying to send a request to target 0
  assign CAN_FIRE_RL_initiator_0_to_target_0 =
             from_initiator_0_taggedReg[76] && !to_target_0_taggedReg[76] &&
             !from_initiator_0_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_0_to_target_0 =
             CAN_FIRE_RL_initiator_0_to_target_0 &&
             !WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_initiator_1_to_target_0
  //   This rule will fire whenever initiator 1 is
  //   trying to send a request to target 0
  assign CAN_FIRE_RL_initiator_1_to_target_0 =
             from_initiator_1_taggedReg[76] && !to_target_0_taggedReg[76] &&
             !from_initiator_1_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_1_to_target_0 =
             CAN_FIRE_RL_initiator_1_to_target_0 &&
             !WILL_FIRE_RL_initiator_0_to_target_0 &&
             !WILL_FIRE_RL_both_initiators_to_target_0 ;

  // rule RL_both_initiators_to_target_1
  //   This rule will fire whenever both initiators are
  //   trying to send a request to target 1
  assign WILL_FIRE_RL_both_initiators_to_target_1 =
             !to_target_1_taggedReg[76] && from_initiator_0_taggedReg[76] &&
             from_initiator_1_taggedReg[76] &&
             from_initiator_0_taggedReg[32] &&
             from_initiator_1_taggedReg[32] ;
  assign CAN_FIRE_RL_both_initiators_to_target_1 =
             WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_initiator_0_to_target_1
  //   This rule will fire whenever initiator 0 is
  //   trying to send a request to target 1
  assign CAN_FIRE_RL_initiator_0_to_target_1 =
             !to_target_1_taggedReg[76] && from_initiator_0_taggedReg[76] &&
             from_initiator_0_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_0_to_target_1 =
             CAN_FIRE_RL_initiator_0_to_target_1 &&
             !WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_initiator_1_to_target_1
  //   This rule will fire whenever initiator 1 is
  //   trying to send a request to target 1
  assign CAN_FIRE_RL_initiator_1_to_target_1 =
             from_initiator_1_taggedReg[76] && !to_target_1_taggedReg[76] &&
             from_initiator_1_taggedReg[32] ;
  assign WILL_FIRE_RL_initiator_1_to_target_1 =
             CAN_FIRE_RL_initiator_1_to_target_1 &&
             !WILL_FIRE_RL_initiator_0_to_target_1 &&
             !WILL_FIRE_RL_both_initiators_to_target_1 ;

  // rule RL_both_targets_to_initiator_0
  //   This rule will fire whenever both targets are
  //   trying to send a response to initiator 0
  assign WILL_FIRE_RL_both_targets_to_initiator_0 =
             from_target_0_taggedReg_8_BIT_44_9_OR_from_tar_ETC___d80 &&
             IF_from_target_0_rw_enq_whas__0_THEN_NOT_from__ETC___d244 &&
             IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d245 ;
  assign CAN_FIRE_RL_both_targets_to_initiator_0 =
             WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_target_0_to_initiator_0
  //   This rule will fire whenever target 0 is
  //   trying to send a response to initiator 0
  assign CAN_FIRE_RL_target_0_to_initiator_0 =
             (from_target_0_taggedReg[44] || from_target_0_rw_enq$whas) &&
             (!to_initiator_0_taggedReg[44] || to_initiator_0_pw_deq$whas) &&
             IF_from_target_0_rw_enq_whas__0_THEN_NOT_from__ETC___d244 ;
  assign WILL_FIRE_RL_target_0_to_initiator_0 =
             CAN_FIRE_RL_target_0_to_initiator_0 &&
             !WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_target_1_to_initiator_0
  //   This rule will fire whenever target 1 is
  //   trying to send a response to initiator 0
  assign CAN_FIRE_RL_target_1_to_initiator_0 =
             (from_target_1_taggedReg[44] || from_target_1_rw_enq$whas) &&
             (!to_initiator_0_taggedReg[44] || to_initiator_0_pw_deq$whas) &&
             IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d245 ;
  assign WILL_FIRE_RL_target_1_to_initiator_0 =
             CAN_FIRE_RL_target_1_to_initiator_0 &&
             !WILL_FIRE_RL_target_0_to_initiator_0 &&
             !WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // rule RL_both_targets_to_initiator_1
  //   This rule will fire whenever both targets are
  //   trying to send a response to initiator 1
  assign WILL_FIRE_RL_both_targets_to_initiator_1 =
             NOT_to_initiator_1_taggedReg_BIT_44_OR_to_init_ETC___d58 &&
             IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236 &&
             IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d234 ;
  assign CAN_FIRE_RL_both_targets_to_initiator_1 =
             WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_target_0_to_initiator_1
  //   This rule will fire whenever target 0 is
  //   trying to send a response to initiator 1
  assign CAN_FIRE_RL_target_0_to_initiator_1 =
             (!to_initiator_1_taggedReg[44] || to_initiator_1_pw_deq$whas) &&
             (from_target_0_taggedReg[44] || from_target_0_rw_enq$whas) &&
             IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236 ;
  assign WILL_FIRE_RL_target_0_to_initiator_1 =
             CAN_FIRE_RL_target_0_to_initiator_1 &&
             !WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_target_1_to_initiator_1
  //   This rule will fire whenever target 1 is
  //   trying to send a response to initiator 1
  assign CAN_FIRE_RL_target_1_to_initiator_1 =
             (from_target_1_taggedReg[44] || from_target_1_rw_enq$whas) &&
             (!to_initiator_1_taggedReg[44] || to_initiator_1_pw_deq$whas) &&
             IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d234 ;
  assign WILL_FIRE_RL_target_1_to_initiator_1 =
             CAN_FIRE_RL_target_1_to_initiator_1 &&
             !WILL_FIRE_RL_target_0_to_initiator_1 &&
             !WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // rule RL_from_target_1_rule_deq
  assign WILL_FIRE_RL_from_target_1_rule_deq =
             WILL_FIRE_RL_both_targets_to_initiator_0 &&
             !to_initiator_0_round_robin ||
             WILL_FIRE_RL_both_targets_to_initiator_1 &&
             !to_initiator_1_round_robin ||
             WILL_FIRE_RL_target_1_to_initiator_0 ||
             WILL_FIRE_RL_target_1_to_initiator_1 ;
  assign CAN_FIRE_RL_from_target_1_rule_deq =
             WILL_FIRE_RL_from_target_1_rule_deq ;

  // rule RL_from_target_1_rule_enq
  assign WILL_FIRE_RL_from_target_1_rule_enq =
             from_target_1_rw_enq$whas &&
             !WILL_FIRE_RL_from_target_1_rule_deq ;
  assign CAN_FIRE_RL_from_target_1_rule_enq =
             WILL_FIRE_RL_from_target_1_rule_enq ;

  // rule RL_from_target_0_rule_deq
  assign WILL_FIRE_RL_from_target_0_rule_deq =
             WILL_FIRE_RL_both_targets_to_initiator_1 &&
             to_initiator_1_round_robin ||
             WILL_FIRE_RL_both_targets_to_initiator_0 &&
             to_initiator_0_round_robin ||
             WILL_FIRE_RL_target_0_to_initiator_0 ||
             WILL_FIRE_RL_target_0_to_initiator_1 ;
  assign CAN_FIRE_RL_from_target_0_rule_deq =
             WILL_FIRE_RL_from_target_0_rule_deq ;

  // rule RL_to_target_1_rule_deq
  assign WILL_FIRE_RL_to_target_1_rule_deq =
             target_1_master_req_reqAccept_accept &&
             (to_target_1_taggedReg[76] || to_target_1_rw_enq$whas) ;
  assign CAN_FIRE_RL_to_target_1_rule_deq =
             WILL_FIRE_RL_to_target_1_rule_deq ;

  // rule RL_from_target_0_rule_enq
  assign WILL_FIRE_RL_from_target_0_rule_enq =
             from_target_0_rw_enq$whas &&
             !WILL_FIRE_RL_from_target_0_rule_deq ;
  assign CAN_FIRE_RL_from_target_0_rule_enq =
             WILL_FIRE_RL_from_target_0_rule_enq ;

  // rule RL_to_target_1_rule_enq
  assign WILL_FIRE_RL_to_target_1_rule_enq =
             to_target_1_rw_enq$whas && !WILL_FIRE_RL_to_target_1_rule_deq ;
  assign CAN_FIRE_RL_to_target_1_rule_enq =
             WILL_FIRE_RL_to_target_1_rule_enq ;

  // rule RL_to_target_0_rule_deq
  assign WILL_FIRE_RL_to_target_0_rule_deq =
             target_0_master_req_reqAccept_accept &&
             (to_target_0_taggedReg[76] || to_target_0_rw_enq$whas) ;
  assign CAN_FIRE_RL_to_target_0_rule_deq =
             WILL_FIRE_RL_to_target_0_rule_deq ;

  // rule RL_to_target_0_rule_enq
  assign WILL_FIRE_RL_to_target_0_rule_enq =
             to_target_0_rw_enq$whas && !WILL_FIRE_RL_to_target_0_rule_deq ;
  assign CAN_FIRE_RL_to_target_0_rule_enq =
             WILL_FIRE_RL_to_target_0_rule_enq ;

  // rule RL_to_initiator_1_rule_update_final
  assign WILL_FIRE_RL_to_initiator_1_rule_update_final =
             to_initiator_1_rw_enq$whas || to_initiator_1_pw_deq$whas ;
  assign CAN_FIRE_RL_to_initiator_1_rule_update_final =
             WILL_FIRE_RL_to_initiator_1_rule_update_final ;

  // rule RL_to_initiator_0_rule_update_final
  assign WILL_FIRE_RL_to_initiator_0_rule_update_final =
             to_initiator_0_rw_enq$whas || to_initiator_0_pw_deq$whas ;
  assign CAN_FIRE_RL_to_initiator_0_rule_update_final =
             WILL_FIRE_RL_to_initiator_0_rule_update_final ;

  // rule RL_from_initiator_1_rule_update_final
  assign WILL_FIRE_RL_from_initiator_1_rule_update_final =
             from_initiator_1_rw_enq$whas || from_initiator_1_pw_deq$whas ;
  assign CAN_FIRE_RL_from_initiator_1_rule_update_final =
             WILL_FIRE_RL_from_initiator_1_rule_update_final ;

  // rule RL_from_initiator_0_rule_update_final
  assign WILL_FIRE_RL_from_initiator_0_rule_update_final =
             from_initiator_0_rw_enq$whas || from_initiator_0_pw_deq$whas ;
  assign CAN_FIRE_RL_from_initiator_0_rule_update_final =
             WILL_FIRE_RL_from_initiator_0_rule_update_final ;

  // inputs to muxes for submodule ports
  assign MUX_from_target_0_taggedReg$write_1__VAL_1 =
             { 1'd1, target_0_master_resp_putResp_resp } ;
  assign MUX_from_target_1_taggedReg$write_1__VAL_1 =
             { 1'd1, target_1_master_resp_putResp_resp } ;
  assign MUX_to_target_0_rw_enq$wset_1__VAL_1 =
             to_target_0_round_robin ?
               from_initiator_0_taggedReg[75:0] :
               from_initiator_1_taggedReg[75:0] ;
  assign MUX_to_target_1_rw_enq$wset_1__VAL_1 =
             to_target_1_round_robin ?
               from_initiator_0_taggedReg[75:0] :
               from_initiator_1_taggedReg[75:0] ;
  assign MUX_to_target_1_taggedReg$write_1__VAL_1 = { 1'd1, _x__h1018 } ;
  assign MUX_to_target_0_taggedReg$write_1__VAL_1 =
             { 1'd1, to_target_0_rw_enq$wget } ;
  assign MUX_to_initiator_0_rw_enq$wset_1__VAL_1 =
             to_initiator_0_round_robin ?
               IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235 :
               IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237 ;
  assign MUX_to_initiator_1_rw_enq$wset_1__VAL_1 =
             to_initiator_1_round_robin ?
               IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235 :
               IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237 ;

  // inlined wires
  assign from_initiator_0_pw_deq$whas =
             WILL_FIRE_RL_both_initiators_to_target_1 &&
             to_target_1_round_robin ||
             WILL_FIRE_RL_both_initiators_to_target_0 &&
             to_target_0_round_robin ||
             WILL_FIRE_RL_initiator_0_to_target_0 ||
             WILL_FIRE_RL_initiator_0_to_target_1 ;
  assign from_initiator_0_rw_enq$whas =
             initiator_0_slave_req_putReq_req[75:74] != 2'd0 &&
             x_initiator_0_slave_req_reqAccept__h2557 ;
  assign from_initiator_1_pw_deq$whas =
             WILL_FIRE_RL_both_initiators_to_target_0 &&
             !to_target_0_round_robin ||
             WILL_FIRE_RL_both_initiators_to_target_1 &&
             !to_target_1_round_robin ||
             WILL_FIRE_RL_initiator_1_to_target_0 ||
             WILL_FIRE_RL_initiator_1_to_target_1 ;
  assign from_initiator_1_rw_enq$whas =
             initiator_1_slave_req_putReq_req[75:74] != 2'd0 &&
             (!from_initiator_1_taggedReg[76] ||
              from_initiator_1_pw_deq$whas) ;
  assign to_initiator_0_pw_deq$whas =
             initiator_0_slave_resp_respAccept_accept &&
             to_initiator_0_taggedReg[44] ;
  assign to_initiator_1_pw_deq$whas =
             initiator_1_slave_resp_respAccept_accept &&
             to_initiator_1_taggedReg[44] ;
  always@(WILL_FIRE_RL_both_initiators_to_target_0 or
          MUX_to_target_0_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_initiator_0_to_target_0 or
          from_initiator_0_taggedReg or
          WILL_FIRE_RL_initiator_1_to_target_0 or from_initiator_1_taggedReg)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_initiators_to_target_0:
          to_target_0_rw_enq$wget = MUX_to_target_0_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_initiator_0_to_target_0:
          to_target_0_rw_enq$wget = from_initiator_0_taggedReg[75:0];
      WILL_FIRE_RL_initiator_1_to_target_0:
          to_target_0_rw_enq$wget = from_initiator_1_taggedReg[75:0];
      default: to_target_0_rw_enq$wget =
                   76'hAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_target_0_rw_enq$whas =
             WILL_FIRE_RL_both_initiators_to_target_0 ||
             WILL_FIRE_RL_initiator_0_to_target_0 ||
             WILL_FIRE_RL_initiator_1_to_target_0 ;
  assign to_target_1_rw_enq$whas =
             WILL_FIRE_RL_both_initiators_to_target_1 ||
             WILL_FIRE_RL_initiator_0_to_target_1 ||
             WILL_FIRE_RL_initiator_1_to_target_1 ;
  assign from_target_0_rw_enq$whas =
             target_0_master_resp_putResp_resp[43] &&
             x_target_0_master_resp_respAccept__h2567 ;
  assign from_target_1_rw_enq$whas =
             target_1_master_resp_putResp_resp[43] &&
             x_target_1_master_resp_respAccept__h2571 ;
  always@(WILL_FIRE_RL_both_targets_to_initiator_0 or
          MUX_to_initiator_0_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_target_0_to_initiator_0 or
          IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235 or
          WILL_FIRE_RL_target_1_to_initiator_0 or
          IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_targets_to_initiator_0:
          to_initiator_0_rw_enq$wget =
              MUX_to_initiator_0_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_target_0_to_initiator_0:
          to_initiator_0_rw_enq$wget =
              IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235;
      WILL_FIRE_RL_target_1_to_initiator_0:
          to_initiator_0_rw_enq$wget =
              IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237;
      default: to_initiator_0_rw_enq$wget =
                   44'hAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_initiator_0_rw_enq$whas =
             WILL_FIRE_RL_both_targets_to_initiator_0 ||
             WILL_FIRE_RL_target_0_to_initiator_0 ||
             WILL_FIRE_RL_target_1_to_initiator_0 ;
  always@(WILL_FIRE_RL_both_targets_to_initiator_1 or
          MUX_to_initiator_1_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_target_0_to_initiator_1 or
          IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235 or
          WILL_FIRE_RL_target_1_to_initiator_1 or
          IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_targets_to_initiator_1:
          to_initiator_1_rw_enq$wget =
              MUX_to_initiator_1_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_target_0_to_initiator_1:
          to_initiator_1_rw_enq$wget =
              IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235;
      WILL_FIRE_RL_target_1_to_initiator_1:
          to_initiator_1_rw_enq$wget =
              IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237;
      default: to_initiator_1_rw_enq$wget =
                   44'hAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign to_initiator_1_rw_enq$whas =
             WILL_FIRE_RL_both_targets_to_initiator_1 ||
             WILL_FIRE_RL_target_0_to_initiator_1 ||
             WILL_FIRE_RL_target_1_to_initiator_1 ;

  // register from_initiator_0_taggedReg
  assign from_initiator_0_taggedReg$D_IN =
             { from_initiator_0_rw_enq$whas,
               initiator_0_slave_req_putReq_req } ;
  assign from_initiator_0_taggedReg$EN =
             WILL_FIRE_RL_from_initiator_0_rule_update_final ;

  // register from_initiator_1_taggedReg
  assign from_initiator_1_taggedReg$D_IN =
             { from_initiator_1_rw_enq$whas,
               initiator_1_slave_req_putReq_req } ;
  assign from_initiator_1_taggedReg$EN =
             WILL_FIRE_RL_from_initiator_1_rule_update_final ;

  // register from_target_0_taggedReg
  assign from_target_0_taggedReg$D_IN =
             WILL_FIRE_RL_from_target_0_rule_enq ?
               MUX_from_target_0_taggedReg$write_1__VAL_1 :
               45'h0AAAAAAAAAAA ;
  assign from_target_0_taggedReg$EN =
             WILL_FIRE_RL_from_target_0_rule_enq ||
             WILL_FIRE_RL_from_target_0_rule_deq ;

  // register from_target_1_taggedReg
  assign from_target_1_taggedReg$D_IN =
             WILL_FIRE_RL_from_target_1_rule_enq ?
               MUX_from_target_1_taggedReg$write_1__VAL_1 :
               45'h0AAAAAAAAAAA ;
  assign from_target_1_taggedReg$EN =
             WILL_FIRE_RL_from_target_1_rule_enq ||
             WILL_FIRE_RL_from_target_1_rule_deq ;

  // register to_initiator_0_round_robin
  assign to_initiator_0_round_robin$D_IN = !to_initiator_0_round_robin ;
  assign to_initiator_0_round_robin$EN =
             WILL_FIRE_RL_both_targets_to_initiator_0 ;

  // register to_initiator_0_taggedReg
  assign to_initiator_0_taggedReg$D_IN =
             { to_initiator_0_rw_enq$whas, to_initiator_0_rw_enq$wget } ;
  assign to_initiator_0_taggedReg$EN =
             WILL_FIRE_RL_to_initiator_0_rule_update_final ;

  // register to_initiator_1_round_robin
  assign to_initiator_1_round_robin$D_IN = !to_initiator_1_round_robin ;
  assign to_initiator_1_round_robin$EN =
             WILL_FIRE_RL_both_targets_to_initiator_1 ;

  // register to_initiator_1_taggedReg
  assign to_initiator_1_taggedReg$D_IN =
             { to_initiator_1_rw_enq$whas, to_initiator_1_rw_enq$wget } ;
  assign to_initiator_1_taggedReg$EN =
             WILL_FIRE_RL_to_initiator_1_rule_update_final ;

  // register to_target_0_round_robin
  assign to_target_0_round_robin$D_IN = !to_target_0_round_robin ;
  assign to_target_0_round_robin$EN =
             WILL_FIRE_RL_both_initiators_to_target_0 ;

  // register to_target_0_taggedReg
  assign to_target_0_taggedReg$D_IN =
             WILL_FIRE_RL_to_target_0_rule_enq ?
               MUX_to_target_0_taggedReg$write_1__VAL_1 :
               77'h0AAAAAAAAAAAAAAAAAAA ;
  assign to_target_0_taggedReg$EN =
             WILL_FIRE_RL_to_target_0_rule_enq ||
             WILL_FIRE_RL_to_target_0_rule_deq ;

  // register to_target_1_round_robin
  assign to_target_1_round_robin$D_IN = !to_target_1_round_robin ;
  assign to_target_1_round_robin$EN =
             WILL_FIRE_RL_both_initiators_to_target_1 ;

  // register to_target_1_taggedReg
  assign to_target_1_taggedReg$D_IN =
             WILL_FIRE_RL_to_target_1_rule_enq ?
               MUX_to_target_1_taggedReg$write_1__VAL_1 :
               77'h0AAAAAAAAAAAAAAAAAAA ;
  assign to_target_1_taggedReg$EN =
             WILL_FIRE_RL_to_target_1_rule_enq ||
             WILL_FIRE_RL_to_target_1_rule_deq ;

  // remaining internal signals
  assign IF_from_target_0_rw_enq_whas__0_THEN_NOT_from__ETC___d244 =
             from_target_0_rw_enq$whas ?
               !target_0_master_resp_putResp_resp[32] :
               !from_target_0_taggedReg[32] ;
  assign IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d235 =
             { from_target_0_rw_enq$whas ?
                 target_0_master_resp_putResp_resp[43] :
                 from_target_0_taggedReg[43],
               IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d280 } ;
  assign IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236 =
             from_target_0_rw_enq$whas ?
               target_0_master_resp_putResp_resp[32] :
               from_target_0_taggedReg[32] ;
  assign IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d280 =
             { from_target_0_rw_enq$whas ?
                 target_0_master_resp_putResp_resp[42:33] :
                 from_target_0_taggedReg[42:33],
               IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d285 } ;
  assign IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d285 =
             { IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236,
               from_target_0_rw_enq$whas ?
                 target_0_master_resp_putResp_resp[31:0] :
                 from_target_0_taggedReg[31:0] } ;
  assign IF_from_target_1_rw_enq_whas_THEN_NOT_from_tar_ETC___d245 =
             from_target_1_rw_enq$whas ?
               !target_1_master_resp_putResp_resp[32] :
               !from_target_1_taggedReg[32] ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d234 =
             from_target_1_rw_enq$whas ?
               target_1_master_resp_putResp_resp[32] :
               from_target_1_taggedReg[32] ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d237 =
             { from_target_1_rw_enq$whas ?
                 target_1_master_resp_putResp_resp[43] :
                 from_target_1_taggedReg[43],
               IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d279 } ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d279 =
             { from_target_1_rw_enq$whas ?
                 target_1_master_resp_putResp_resp[42:33] :
                 from_target_1_taggedReg[42:33],
               IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d286 } ;
  assign IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d286 =
             { IF_from_target_1_rw_enq_whas_THEN_from_target__ETC___d234,
               from_target_1_rw_enq$whas ?
                 target_1_master_resp_putResp_resp[31:0] :
                 from_target_1_taggedReg[31:0] } ;
  assign NOT_to_initiator_1_taggedReg_BIT_44_OR_to_init_ETC___d58 =
             (!to_initiator_1_taggedReg[44] || to_initiator_1_pw_deq$whas) &&
             (from_target_0_taggedReg[44] || from_target_0_rw_enq$whas) &&
             (IF_from_target_0_rw_enq_whas__0_THEN_NOT_from__ETC___d244 ||
              from_target_1_taggedReg[44] ||
              from_target_1_rw_enq$whas) &&
             (to_initiator_1_round_robin || from_target_1_taggedReg[44] ||
              from_target_1_rw_enq$whas) ;
  assign from_target_0_taggedReg_8_BIT_44_9_OR_from_tar_ETC___d80 =
             (from_target_0_taggedReg[44] || from_target_0_rw_enq$whas) &&
             (!to_initiator_0_taggedReg[44] || to_initiator_0_pw_deq$whas) &&
             (IF_from_target_0_rw_enq_whas__0_THEN_from_targ_ETC___d236 ||
              from_target_1_taggedReg[44] ||
              from_target_1_rw_enq$whas) &&
             (to_initiator_0_round_robin || from_target_1_taggedReg[44] ||
              from_target_1_rw_enq$whas) ;
  assign target_0_master_req_getReq_reqAddr__h2786 =
             to_target_0_rw_enq$whas ?
               to_target_0_rw_enq$wget[63:32] :
               to_target_0_taggedReg[63:32] ;
  assign target_0_master_req_getReq_reqData__h2787 =
             to_target_0_rw_enq$whas ?
               to_target_0_rw_enq$wget[31:0] :
               to_target_0_taggedReg[31:0] ;
  assign target_0_master_req_getReq_reqInfo__h2785 =
             to_target_0_rw_enq$whas ?
               to_target_0_rw_enq$wget[73:64] :
               to_target_0_taggedReg[73:64] ;
  assign target_1_master_req_getReq_reqAddr__h2890 =
             to_target_1_rw_enq$whas ?
               _x__h1018[63:32] :
               to_target_1_taggedReg[63:32] ;
  assign target_1_master_req_getReq_reqData__h2891 =
             to_target_1_rw_enq$whas ?
               _x__h1018[31:0] :
               to_target_1_taggedReg[31:0] ;
  assign target_1_master_req_getReq_reqInfo__h2889 =
             to_target_1_rw_enq$whas ?
               _x__h1018[73:64] :
               to_target_1_taggedReg[73:64] ;
  assign x_initiator_0_slave_req_reqAccept__h2557 =
             !from_initiator_0_taggedReg[76] || from_initiator_0_pw_deq$whas ;
  assign x_target_0_master_resp_respAccept__h2567 =
             !from_target_0_taggedReg[44] ;
  assign x_target_1_master_resp_respAccept__h2571 =
             !from_target_1_taggedReg[44] ;
  always@(WILL_FIRE_RL_both_initiators_to_target_1 or
          MUX_to_target_1_rw_enq$wset_1__VAL_1 or
          WILL_FIRE_RL_initiator_0_to_target_1 or
          from_initiator_0_taggedReg or
          WILL_FIRE_RL_initiator_1_to_target_1 or from_initiator_1_taggedReg)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_both_initiators_to_target_1:
          _x__h1018 = MUX_to_target_1_rw_enq$wset_1__VAL_1;
      WILL_FIRE_RL_initiator_0_to_target_1:
          _x__h1018 = from_initiator_0_taggedReg[75:0];
      WILL_FIRE_RL_initiator_1_to_target_1:
          _x__h1018 = from_initiator_1_taggedReg[75:0];
      default: _x__h1018 = 76'hAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(to_target_0_rw_enq$whas or
          to_target_0_rw_enq$wget or to_target_0_taggedReg)
  case (1'b1)
    to_target_0_rw_enq$whas:
        IF_to_target_0_taggedReg_07_BIT_76_08_OR_to_ta_ETC___d265 =
            to_target_0_rw_enq$wget[75:74];
    to_target_0_taggedReg[76] || to_target_0_rw_enq$whas:
        IF_to_target_0_taggedReg_07_BIT_76_08_OR_to_ta_ETC___d265 =
            to_target_0_taggedReg[75:74];
    default: IF_to_target_0_taggedReg_07_BIT_76_08_OR_to_ta_ETC___d265 = 2'd0;
  endcase
  always@(to_target_1_rw_enq$whas or _x__h1018 or to_target_1_taggedReg)
  case (1'b1)
    to_target_1_rw_enq$whas:
        IF_to_target_1_taggedReg_7_BIT_76_8_OR_to_targ_ETC___d263 =
            _x__h1018[75:74];
    to_target_1_taggedReg[76] || to_target_1_rw_enq$whas:
        IF_to_target_1_taggedReg_7_BIT_76_8_OR_to_targ_ETC___d263 =
            to_target_1_taggedReg[75:74];
    default: IF_to_target_1_taggedReg_7_BIT_76_8_OR_to_targ_ETC___d263 = 2'd0;
  endcase

  // handling of inlined registers
  
  always@(posedge CLK)
  begin
    if (!RST_N)
      begin
        from_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        from_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        from_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        from_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        to_initiator_0_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
        to_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        to_initiator_1_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
        to_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY 45'h0AAAAAAAAAAA;
        to_target_0_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
        to_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
        to_target_1_round_robin <= `BSV_ASSIGNMENT_DELAY 1'd0;
        to_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
            77'h0AAAAAAAAAAAAAAAAAAA;
      end
    else
      begin
        if (from_initiator_0_taggedReg$EN)
          from_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
              from_initiator_0_taggedReg$D_IN;
        if (from_initiator_1_taggedReg$EN)
          from_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
              from_initiator_1_taggedReg$D_IN;
        if (from_target_0_taggedReg$EN)
          from_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
              from_target_0_taggedReg$D_IN;
        if (from_target_1_taggedReg$EN)
          from_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
              from_target_1_taggedReg$D_IN;
        if (to_initiator_0_round_robin$EN)
          to_initiator_0_round_robin <= `BSV_ASSIGNMENT_DELAY
              to_initiator_0_round_robin$D_IN;
        if (to_initiator_0_taggedReg$EN)
          to_initiator_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
              to_initiator_0_taggedReg$D_IN;
        if (to_initiator_1_round_robin$EN)
          to_initiator_1_round_robin <= `BSV_ASSIGNMENT_DELAY
              to_initiator_1_round_robin$D_IN;
        if (to_initiator_1_taggedReg$EN)
          to_initiator_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
              to_initiator_1_taggedReg$D_IN;
        if (to_target_0_round_robin$EN)
          to_target_0_round_robin <= `BSV_ASSIGNMENT_DELAY
              to_target_0_round_robin$D_IN;
        if (to_target_0_taggedReg$EN)
          to_target_0_taggedReg <= `BSV_ASSIGNMENT_DELAY
              to_target_0_taggedReg$D_IN;
        if (to_target_1_round_robin$EN)
          to_target_1_round_robin <= `BSV_ASSIGNMENT_DELAY
              to_target_1_round_robin$D_IN;
        if (to_target_1_taggedReg$EN)
          to_target_1_taggedReg <= `BSV_ASSIGNMENT_DELAY
              to_target_1_taggedReg$D_IN;
      end
  end
  
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    from_initiator_0_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    from_initiator_1_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    from_target_0_taggedReg = 45'h0AAAAAAAAAAA;
    from_target_1_taggedReg = 45'h0AAAAAAAAAAA;
    to_initiator_0_round_robin = 1'h0;
    to_initiator_0_taggedReg = 45'h0AAAAAAAAAAA;
    to_initiator_1_round_robin = 1'h0;
    to_initiator_1_taggedReg = 45'h0AAAAAAAAAAA;
    to_target_0_round_robin = 1'h0;
    to_target_0_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
    to_target_1_round_robin = 1'h0;
    to_target_1_taggedReg = 77'h0AAAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkSwitch

        