SNUG 2001
Our Methodology
• Verilog, full synthesis, static timing, simulation/emulation/formal
• 1,2,4,8
•1 conception, 2 implementations, 4 representations, 8 ways to verify
• COT flow
•3rd party std. cells/RAMs, custom RAMs/PLL/DAC/IO
• Historical two designs per technology (~ 1 process/year)
• Priorities : schedule, performance/area
• Multiple, overlapped design teams (3 teams, 2 seasons)
• Constantly evolving methodology, partner with vendors
• Typical 1.5 year schedule would have:
•1-2 months specification
•2-4 months of implementation
•3-9 months of verification
•1-2 months of physical design